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Bit error measurement system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0732303 (1997-02-10)
우선권정보 JP-0102956 (1995-04-04)
국제출원번호 PCT/JP96/004 (1996-02-22)
§371/§102 date 19970210 (19970210)
국제공개번호 WO-9626451 (1996-08-02)
발명자 / 주소
  • Sotome Tetsuo,JPX
  • Nakajima Takayuki,JPX
  • Osawa Kazutaka,JPX
  • Shimawaki Kazuhiro,JPX
  • Shiroyama Kouichi,JPX
출원인 / 주소
  • Advantest Corp., JPX
대리인 / 주소
    Muramatsu & Associates
인용정보 피인용 횟수 : 100  인용 특허 : 0

초록

A bit error measurement system provides means for generating test patterns, multiplexing means and means for specifying and recording a pattern position. In a first aspect, a bit error measurement system has a pattern generator having M channels of pattern generation and a pattern generation control

대표청구항

[ What is claimed is:] [1.] A test pattern generator to be used for a bit error measurement and has a M channel selectable pattern generator to generate selected test patterns, characterized in that said test pattern generator having:a pattern generator having M channels for pattern generation: anda

이 특허를 인용한 특허 (100)

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