초록 ▼

A circuit for suppressing period jitter of the clock output of a ring oscillator caused by supply voltage fluctuations. The ring oscillator includes n identical current controlled delay circuits 26.1-n connected in a ring, and a replica circuit 36 identical to the current controlled delay circuit. T

A circuit for suppressing period jitter of the clock output of a ring oscillator caused by supply voltage fluctuations. The ring oscillator includes n identical current controlled delay circuits 26.1-n connected in a ring, and a replica circuit 36 identical to the current controlled delay circuit. The replica circuit 36 receives a constant input voltage so that its output is always at a high level. A differential amplifier 35 receiving a reference potential Vref is connected in a negative feedback circuit with replica circuit 36, so that the output of the replica circuit 36 is held equal to the reference potential Vref. An output of the negative feedback circuit is also applied to each of the current controlled delay circuits 26.1-n, so that their high level outputs are held equal to the reference potential Vref.

대표청구항 ▼

[ I claim:] [1.] A voltage controlled oscillator in which the frequency of an output signal is variable according to an input voltage signal, comprising:first to nth (n is an odd number) inverters which are cascade-connected cyclically and have the same structures;an (n+1)th inverter which has the s

[ I claim:] [1.] A voltage controlled oscillator in which the frequency of an output signal is variable according to an input voltage signal, comprising:first to nth (n is an odd number) inverters which are cascade-connected cyclically and have the same structures;an (n+1)th inverter which has the same structure as that of each of the first to nth inverters and has an input connected to one of power lines;first to (n+1)th current sources which have the same structures, are provided between the other power line and power input ends of said first to (n+1)th inverters respectively, and supply, to said first to (n+1)th inverters respectively, a current having a magnitude which corresponds to a control signal;a current control circuit for supplying said control signal to said first to (n+1)th current sources according to said input voltage signal;first to (n+1)th bypass circuits which have the same structures, are provided between respective said power input ends of said first to (n+1)th inverters and said one of power lines, and are conducted to bypass currents of said first to (n+1)th current sources; anda bypass control circuit which holds a potential difference between an output of said (n+1)th inverter and said one of power lines to have a predetermined value which is set smaller than a voltage between said one of power lines and said other power line by making said first to (n+1)th bypass circuits conductive when said potential difference exceeds said predetermined value.