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"" 따옴표 내의 구문과 완전히 일치하는 문서만 검색 예) "Transform and Quantization"

특허 상세정보

Tokens-based adaptive video processing arrangement

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-003/14   
미국특허분류(USC) 395/500 ; 395/800.15 ; 395/200.51
출원번호 US-0399898 (1995-03-07)
우선권정보 GB-0004047 (1995-02-28)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Clark
인용정보 피인용 횟수 : 67  인용 특허 : 0
초록

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and ar...

대표
청구항

[ I claim:] [1.] For use with a video decompression system having a plurality of processing stages:a universal adaptation unit in the form of an interactive interfacing token, for control and/or data functions among said processing stages, wherein said unit is dynamically adaptive and causes said processing stages to reconfigure;wherein said system operates on a data stream having a plurality of video formats carried therein, and said unit comprises a plurality of units that contain data encoded in different ones of said video formats, and said units are...

이 특허를 인용한 특허 피인용횟수: 67

  1. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2013028380884.
  2. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2015049015352.
  3. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2014048706916.
  4. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2009107606943.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2015109164952.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543795.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098533431.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
  10. Master, Paul L.; Uvacek, Bohumir. Apparatus and method for adaptive multimedia reception and transmission in communication environments. USP2015049002998.
  11. Hu Yi-Kwang,TWX. Apparatus and method for decoding compressed digital video data. USP2001086282244.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2016059330058.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2014118880849.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2012088250339.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements. USP2017039594723.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2013048412915.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2012078225073.
  18. Farley, Kevin L.; Proctor, James A.. Application specific traffic optimization in a wireless link. USP2017069686713.
  19. Farley, Kevin L.; Proctor, Jr., James A.. Application specific traffic optimization in a wireless link. USP2015129210616.
  20. Morishita, Hiroyuki; Tanaka, Takeshi; Maeda, Masaki; Wakayama, Yorihiko. Array type operation device. USP2009107606996.
  21. Howard, Ric; Katragadda, Ramana V.. Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture. USP2009087577799.
  22. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James. Communications module, device, and method for implementing a system acquisition function. USP2009117620097.
  23. Kasama, Ichiro. Computing apparatus. USP2012048150949.
  24. Master, Paul L.; Watson, John. Configurable hardware based digital imaging apparatus. USP2009107609297.
  25. Scheuermann, W. James; Hogenauer, Eugene B.. Control node for multi-core system. USP20190110185502.
  26. Nagata,Hisashi; Noguchi,Noboru; Mizukata,Katsuya. Data transfer method, image display device and signal line driving circuit, active-matrix substrate. USP2009017474305.
  27. Saito, Tomonobu; Oobayashi, Tsuyoshi; Vu, Khac Tri; Uytterhoeven, Geert; Hostyn, Tom Frans Maurits; Onishi, Manabu; Shimizu, Shunkichi; Nishikawa, Takahiro. Data transmission system, receiving apparatus, and receiving method as well as sending apparatus and sending method. USP2015099148696.
  28. Yu, Jingjian. Error detection method of variable-length coding code stream and decoding and error detection apparatus. USP2017039608671.
  29. Furtek, Frederick Curtis; Master, Paul L.. External memory controller. USP2012098266388.
  30. Furtek, Frederick Curtis; Master, Paul L.. External memory controller node. USP2014078769214.
  31. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077984247.
  32. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077979646.
  33. Scheuermann,Walter James. Hardware implementation of the secure hash standard. USP2009027489779.
  34. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2017059665397.
  35. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2012068200799.
  36. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2010017653710.
  37. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2014078782196.
  38. Master,Paul L.; Hogenauer,Eugene; Scheuermann,Walter James. Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements. USP2008017325123.
  39. Heidari-Bateni, Ghobad; Sambhwani, Sharad D.. Internal synchronization control for adaptive integrated circuitry. USP2012108296764.
  40. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2013058442096.
  41. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2010027668229.
  42. Sambhwani,Sharad; Heidari,Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2009037512173.
  43. Master, Paul L.. Method and system for achieving individualized protected space in an operating system. USP2010027660984.
  44. Master, Paul L.. Method and system for creating and programming an adaptive computing engine. USP2011017865847.
  45. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2015059037834.
  46. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2016079396161.
  47. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2013118589660.
  48. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2010077752419.
  49. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2014078767804.
  50. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2012088249135.
  51. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107809050.
  52. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107822109.
  53. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn. Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information. USP2009017478031.
  54. Michener, James A.; Stanger, Leon J.; Munsell, Michael R.. Methods and apparatus to test receivers. USP2010107817184.
  55. Fung,Kendall H; Su,Hui; Coonen,Dan J. NRZ pipeline servo while reading or writing. USP2006117136239.
  56. Shivji, Shane. Object identifier. USP2014088803894.
  57. Master, Paul L.. Profiling of software and circuit designs utilizing data operation analyses. USP2012098276135.
  58. McCrossan, Joseph; Okada, Tomoyuki; Mochinaga, Kazuhiro. Recording medium, reproduction apparatus, recording method, integrated circuit, program and reproduction method. USP2012108280230.
  59. McCrossan, Joseph; Okada, Tomoyuki; Mochinaga, Kazuhiro. Recording medium, reproduction apparatus, recording method, integrated circuit, program, and reproduction method. USP2013028369690.
  60. McCrossan, Joseph; Okada, Tomoyuki; Mochinaga, Kazuhiro. Recording medium, reproduction apparatus, recording method, integrated circuit, program, and reproduction method. USP2014038682146.
  61. Bailey, Scott A.; Lloyd, Kevin Robert; Kazemian, Peyman. Remote control of a host computer. USP2014088812615.
  62. Master,Paul L.; Watson,John. Storage and delivery of device features. USP2009027493375.
  63. Master, Paul L.; Watson, John. System for adapting device standards after manufacture. USP2009107602740.
  64. Master, Paul L.; Watson, John. System for authorizing functionality in adaptable hardware devices. USP201109E042743.
  65. Gough, Michael L.; Miner, Paul. System for pipelined processing. USP2012108300988.
  66. Gough, Michael L.; Miner, Paul. System, method and article of manufacture for decompressing digital camera sensor data. USP2016099449401.
  67. Katragadda, Ramana; Spoltore, Paul; Howard, Ric. Task definition for specifying resource requirements. USP2012018108656.