초록 ▼

The invention provides a method and system in which a single pin coupled to an integrated circuit (IC) chip is used to enter configuration information at a power-up time or a reset time (collectively referred to herein as a "reset time" or "reset interval"), and is also used to display output inform

The invention provides a method and system in which a single pin coupled to an integrated circuit (IC) chip is used to enter configuration information at a power-up time or a reset time (collectively referred to herein as a "reset time" or "reset interval"), and is also used to display output information during normal operation. The pin is coupled to a memory device, so as to store configuration information received during the reset interval. The pin is also coupled to an output driver controlled by a gate which combines output data with a signal indicating reset time, so as to put the output driver into a high impedance state during reset time when the input configuration data is being stored into the device and to drive the pin with the output value during non-reset times. Thus, a user of the IC may cause the memory to receive configuration information from the pin at power-up or during another reset time, while having the pin output normal data at times other than the reset interval.

대표청구항 ▼

[ What is claimed is:] [1.] Apparatus comprising:an on-chip circuit integrated onto a semiconductor wafer, said circuit comprising a node disposed for coupling to an external pin, said node coupled to a driving circuit, said driving circuit including a transistor coupled between said node and a refe

[ What is claimed is:] [1.] Apparatus comprising:an on-chip circuit integrated onto a semiconductor wafer, said circuit comprising a node disposed for coupling to an external pin, said node coupled to a driving circuit, said driving circuit including a transistor coupled between said node and a reference voltage and a logic gate coupled to a control input for said transistor, said logic gate being coupled to receive said reset signal and to receive a data signal, wherein said driving circuit is coupled to a source of a reset signal, said node is coupled to a memory, and said memory is coupled to said source of a reset signal.