초록 ▼

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: t

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

대표청구항 ▼

[ What is claimed is:] [1.] A method of forming a semiconductor integrated circuit device having a memory array, direct peripheral circuitry and an output buffer circuit, said direct peripheral circuitry including a first MISFET to which a first operating voltage is applied, and said output buffer c

[ What is claimed is:] [1.] A method of forming a semiconductor integrated circuit device having a memory array, direct peripheral circuitry and an output buffer circuit, said direct peripheral circuitry including a first MISFET to which a first operating voltage is applied, and said output buffer circuit including a second MISFET to which a second operating voltage, higher than the first operating voltage, is applied, said method comprising the steps of:providing a semiconductor substrate having a main surface, the semiconductor substrate including a first portion for said first MISFET and a second portion for said second MISFET;forming a first gate insulating film in said first portion and a second gate insulating film in said second portion;forming a first gate electrode on said first gate insulating film in said first portion and a second gate electrode on said second gate insulating film in said second portion, said first and second gate electrodes having side surfaces;introducing first impurities of a first conductivity type into said first and second portions in a self-aligned manner with said first and second gate electrodes, respectively;forming sidewall spacers on said side surfaces of said first and second gate electrodes, said sidewall spacers on said side surfaces of the first gate electrode having a same width as a width of the sidewall spacers on the side surfaces of the second gate electrode; andintroducing second impurities of the first conductivity type into said first and second portions in a self-aligned manner with said sidewall spacers, wherein a length of the second gate electrode is longer than that of said first gate electrode.