초록 ▼

A non-volatile memory latch device includes two PMOS memory cells and a cross-coupled static latch having two PMOS transistors and two NMOS transistors. The floating gates of each PMOS memory cell/transistor pair are coupled together. The control gates of all four PMOS devices are commonly connected

A non-volatile memory latch device includes two PMOS memory cells and a cross-coupled static latch having two PMOS transistors and two NMOS transistors. The floating gates of each PMOS memory cell/transistor pair are coupled together. The control gates of all four PMOS devices are commonly connected to an input. The latch is programmed by applying -3 to -8 volts to the drain of one of the PMOS memory cells, floating the drain of the other PMOS memory cell, and applying 7 to 11 volts to the control gates of all four PMOS devices. The latch is erased by applying 3 to 8 volts to both drains of the PMOS memory cells and -7 to -11 volts to the control gates of all four PMOS devices. Lower programming and erasing voltages are possible with the PMOS latch, as compared with conventional NMOS latches.

대표청구항 ▼

[ We claim:] [1.] A non-volatile latch comprising:a first PMOS memory cell;a second PMOS memory cell; anda cross-coupled static latch comprising third and fourth PMOS memory celsl and first and second NMOS transistors, wherein the floating gates of said first and third PMOS memory cells are coupled

[ We claim:] [1.] A non-volatile latch comprising:a first PMOS memory cell;a second PMOS memory cell; anda cross-coupled static latch comprising third and fourth PMOS memory celsl and first and second NMOS transistors, wherein the floating gates of said first and third PMOS memory cells are coupled together and the floating gates of said second and fourth PMOS memory cells are coupled together.