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Method of fabricating a barrier against metal diffusion 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0696270 (1996-08-13)
발명자 / 주소
  • Gardner Donald S.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman
인용정보 피인용 횟수 : 54  인용 특허 : 19

초록

A method of forming a barrier layer for preventing the diffusion of a metal interconnect through an interlayer dielectric of an integrated circuit and to act as an etch stop. A thin metal layer is formed on the interlayer dielectric and then oxidized to form a metal-oxide barrier layer.

대표청구항 ▼

[ I claim:] [1.] A method of forming a barrier layer for preventing the diffusion of a metal interconnect through an interlayer dielectric of an integrated circuit, said method comprising the steps of:forming a first metal layer on said interlayer dielectric;oxidizing said first metal layer to form

이 특허에 인용된 특허 (19)

  1. Doan Trung T. (Boise ID) Thakur Randhir P. S. (Boise ID) Liu Yauh-Ching (Boise ID), Approach to avoid buckling in BPSG by using an intermediate barrier layer.
    상세보기
  2. Sun Shih W. (Austin TX) Lee Jen-Jiang (Austin TX), Device metallization, device and method.
    상세보기
  3. Lim Sheldon C. P. (Sunnyvale CA) Hellstrom Julie W. (Santa Clara CA) Yen Ting P. (Fremont CA), Fabrication method using oxidation to control size of fusible link.
    상세보기
  4. Schmidt Conrad (Meckesheim DE) Bunger Gustav (Mannheim DE) Weiss Paul (Oftersheim DE), Insulators with increased surface conductivity and method for increasing the conductivity on surfaces of insulators havi.
    상세보기
  5. Kikkawa Takamaro (Tokyo JPX), Integrated circuit device with an improved interconnection line.
    상세보기
  6. Abt Norman E. (Burlingame CA) Moazzami Reza (Oakland CA) Nissan-Cohen Yoav (Zichren Ya\akov ILX), Method for forming a ceramic oxide capacitor having barrier layers.
    상세보기
  7. Ikeda Yujiro (Ikoma JPX) Kinoshita Takao (Tenri JPX), Method for forming a contact plug.
    상세보기
  8. Thompson Charles E. (Carlsbad CA), Method for forming an aluminum interconnect structure on an integrated circuit chip.
    상세보기
  9. Chan Chung (W. Newton MA), Method for metal ion implantation using multiple pulsed arcs.
    상세보기
  10. Kaw Ravindhar K. (San Jose CA), Monolithic semiconductor chip interconnection technique and arrangement.
    상세보기
  11. Labunov Vladimir A. (Minsk BYX) Sokol Vitaly A. (Minsk BYX) Parkun Vladimir M. (Minsk BYX) Vorob\yova Alla I. (Minsk BYX), Process for making multilevel interconnections of electronic components.
    상세보기
  12. Butt Sheldon H. (Godfrey IL) Cherukuri Satyam C. (West Haven CT), Process for producing a hermetically sealed package for an electrical component containing a low amount of oxygen and wa.
    상세보기
  13. Lim Sheldon C. P. (Sunnyvale CA) Hellstrom Julie W. (Santa Clara CA) Yen Ting P. (Fremont CA), Programmable semiconductor integrated circuits having fusible links.
    상세보기
  14. Wei Che-Chia (Plano TX), Self-aligned contact process.
    상세보기
  15. Yonezawa, Toshio; Aoyama, Masaharu, Semiconductor device.
    상세보기
  16. Mochizuki Hiroshi (Hyogo JPX) Tamaki Reiji (Hyogo JPX) Arima Junichi (Hyogo JPX) Ikegami Masaaki (Hyogo JPX) Tanaka Eisuke (Hyogo JPX) Saito Kenji (Hyogo JPX), Semiconductor device and method for making the same.
    상세보기
  17. Hirata Yoshihiro (Hyogo JPX) Tamaki Reiji (Hyogo JPX) Noguchi Takeshi (Hyogo JPX) Arima Junichi (Hyogo JPX) Saitoh Kenji (Hyogo JPX) Harada Shigeru (Hyogo JPX), Semiconductor device and method of manufacturing thereof.
    상세보기
  18. Tsuneoka Masatoshi (Ohme JPX) Horiuchi Mitsuaki (Hachioji JPX), Semiconductor integrated circuit device.
    상세보기
  19. Chu Wei-Kan (La Grangeville NY) Howard James K. (Fishkill NY) White James F. (Newburgh NY), Thin film structures and method for fabricating same.
    상세보기

이 특허를 인용한 특허 (54)

  1. Padhi, Deenesh; Guggilla, Srinivas; Demos, Alexandros T.; Kumar, Bhaskar; Ren, He; Dash, Priyanka, Aluminum nitride barrier layer.
    상세보기
  2. Brenda D. Kraus ; John T. Moore ; Scott J. DeBoer, Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride.
    상세보기
  3. Kraus Brenda D. ; Moore John T. ; DeBoer Scott J., Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride.
    상세보기
  4. Kraus, Brenda D.; Moore, John T.; DeBoer, Scott J., Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride.
    상세보기
  5. Sambucetti, Carlos Juan; Chen, Xiaomeng; Seo, Soon-Cheon; Agarwala, Birenda Nath; Hu, Chao-Kun; Lustig, Naftali Eliahu; Greco, Stephen Edward, Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect.
    상세보기
  6. Oskam Gerko ; Searson Peter C. ; Vereecken Philippe M. ; Long John G. ; Hoffmann Peter M., Copper metallization structure and method of construction.
    상세보기
  7. Kraus, Brenda D.; Lane, Richard H., DRAM circuitry having storage capacitors which include capacitor dielectric regions comprising aluminum nitride.
    상세보기
  8. Won,Seok Jun, Electrical interconnection, method of forming the electrical interconnection, image sensor having the electrical interconnection and method of manufacturing the image sensor.
    상세보기
  9. You, Young-Sub; Park, Jae-Young; Shin, Won-Shik; Lee, Hyeon-Deok; Im, Ki-Vin; Nam, Seok-Woo; Lim, Hun-Young; Jang, Won-Jun; Hyung, Yong-Woo, Etch stop structure and method of manufacture, and semiconductor device and method of manufacture.
    상세보기
  10. Kraus, Brenda D.; Lane, Richard H., Field emission device having a covering comprising aluminum nitride.
    상세보기
  11. McTeer,Allen, Interconnect structure for use in an integrated circuit.
    상세보기
  12. Jolanta Celinska ; Jeffrey W. Bacon ; Akihiro Matsuda JP; Carlos A. Paz de Araujo, Liquid precursors for aluminum oxide and method making same.
    상세보기
  13. Koga,Keiji, Magnetic memory and manufacturing method thereof.
    상세보기
  14. Morrow, Xiaorong; Leu, Jihperng; Kuhn, Markus; Maiz, Jose A., Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects.
    상세보기
  15. Morrow, Xiaorong; Leu, Jihperng; Kuhn, Markus; Maiz, Jose A., Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects.
    상세보기
  16. Suk-Jae Lee KR, Method for manufacturing a copper interconnection with an aluminum oxide-conductive layer stack barrier layer in semiconductor memory device.
    상세보기
  17. Brenda D. Kraus ; Richard H. Lane, Method of depositing an aluminum nitride comprising layer over a semiconductor substrate.
    상세보기
  18. Brenda D. Kraus ; Richard H. Lane, Method of forming DRAM circuitry, DRAM circuitry, method of forming a field emission device, and field emission device.
    상세보기
  19. McTeer,Allen, Method of forming an interconnect structure for a semiconductor device.
    상세보기
  20. Takashi Kawanoue JP; Tetsuo Matsuda JP; Hisashi Kaneko JP; Tadashi Iijima JP, Method of manufacturing a copper interconnect.
    상세보기
  21. Park Jong-min,KRX ; Lee Sang-woo,KRX ; Yoo Byoung-ju,KRX, Method of manufacturing barrier metal film of semiconductor device and method of manufacturing metal interconnection film of semiconductor device using the same.
    상세보기
  22. Gupta Subhash,SGX ; Ho Paul Kwok Keung,SGX ; Zhou Mei Sheng,SGX ; Chockalingam Ramasamy,SGX, Method to avoid copper contamination during copper etching and CMP.
    상세보기
  23. Kraus, Brenda D.; Lane, Richard H., Methods of forming a field emission device.
    상세보기
  24. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
    상세보기
  25. Helneder, Johann; Schwerd, Markus; Goebel, Thomas; Mitchell, Andrea; Koerner, Heinrich; Hommel, Martina, Process for producing a multifunctional dielectric layer on a substrate.
    상세보기
  26. Sugai Kazumi,JPX, Process for production of semiconductor device having an insulating film of low dielectric constant.
    상세보기
  27. Gardner Mark I. ; Gilmer Mark C., Semiconductor device having in-doped indium oxide etch stop.
    상세보기
  28. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; He, Zhong-Xiang; Muzzy, Christopher D.; Sauter, Wolfgang; Sullivan, Timothy D., Semiconductor structures and methods of manufacture.
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  29. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; He, Zhong-Xiang; Muzzy, Christopher D.; Sauter, Wolfgang; Sullivan, Timothy D., Semiconductor structures and methods of manufacture.
    상세보기
  30. Chinthakindi,Anil K.; Eshun,Ebenezer E., Thin film resistor with current density enhancing layer (CDEL).
    상세보기
  31. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  32. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  33. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  34. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  35. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  36. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  37. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  38. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  39. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  40. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  41. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  42. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  43. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  44. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  45. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  46. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  47. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  48. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  49. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  50. Lin,Mou Shiung, Top layers of metal for high performance IC's.
    상세보기
  51. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  52. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  53. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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  54. McTeer, Allen, Use of AIN as cooper passivation layer and thermal conductor.
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