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Advanced copper interconnect system that is compatible with existing IC wire bonding technology 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/60
출원번호 US-0564695 (1995-11-29)
발명자 / 주소
  • Cheung Robin W.
  • Lin Ming-Ren
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Saywer & Associates
인용정보 피인용 횟수 : 43  인용 특허 : 0

초록

A process is provided which enables electrical connection to be formed between gold and aluminum wires and copper interconnects. Conventional techniques for wire bonding are ineffective for bonding gold wires or aluminum wires to copper pads or copper interconnects. A process is provided to modify t

대표청구항

[ what is claimed is:] [1.] A process for forming electrical connection between metal wires and metal interconnects which cannot otherwise be bonded to form electrical contact therebetween, said metal wires and said metal interconnects supported over an integrated circuit structure, said metal inter

이 특허를 인용한 특허 (43)

  1. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
  2. Wang, Chung Yu; Lee, Chien-Hsiun, Aluminum cap for reducing scratch and wire-bond bridging of bond pads.
  3. Tseng, Horng-Huei; Hu, Chenming, Aluminum-based interconnection in bond pad layer.
  4. Yu, Chen-Hua; Tseng, Horng-Huei, Bonding structure and fabrication thereof.
  5. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  6. Saran, Mukul; Martin, Charles A.; Cox, Ronald H., Fine pitch system and method for reinforcing bond pads in semiconductor devices.
  7. Ryan,Vivian, Integrated circuit having bond pad with improved thermal and mechanical properties.
  8. Rhodes,Howard E., Local multilayered metallization.
  9. Rhodes,Howard E., Local multilayered metallization.
  10. Iacoponi, John A., Method and apparatus for forming an under bump metallurgy layer.
  11. Stierman, Roger J.; Moore, Thomas M.; Shinn, Gregory B., Method for reworking metal layers on integrated circuit bond pads.
  12. Stierman, Roger J.; Moore, Thomas M.; Shinn, Gregory B., Method for reworking metal layers on integrated circuit bond pads.
  13. Kwok Keung Paul Ho SG; Simon Chooi SG; Yi Xu SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding.
  14. Ho, Kwok Keung Paul; Chooi, Simon; Xu, Yi; Aliyu, Yakub; Zhou, Mei Sheng; Sudijono, John Leonard; Gupta, Subhash; Roy, Sudipto Ranendra, Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding.
  15. Kwok Keung Paul Ho SG; Yi Xu SG; Simon Chooi SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of displacement reaction to form a conductive cap layer for flip-chip, COB, and micro metal bonding.
  16. Huang Yimin,TWX ; Yew Tri-Rung,TWX, Method of forming bonding pad.
  17. Chen Sheng-Hsiung,TWX, Method of improving copper pad adhesion.
  18. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  19. Sheng-Hsiung Chen TW; Fan Keng Yang TW, Method of improving pad metal adhesion.
  20. Yabu Toshiki,JPX ; Segawa Mizuki,JPX, Method of making a semiconductor device.
  21. Jang Syun-Ming,TWX ; Liang Mong-Song,TWX, Method to improve the adhesion of a molding compound to a semiconductor chip comprised with copper damascene structures.
  22. Chungpaiboonpatana Surasit ; Davidson Craig, Microelectronic interconnect structures and methods for forming the same.
  23. Edelstein Daniel Charles ; McGahay Vincent ; Nye ; III Henry A. ; Ottey Brian George Reid ; Price William H., Robust interconnect structure.
  24. Tsu Shih TW; Chen-Hua Yu TW, Self stop aluminum pad for copper process.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  26. Timothy W. Ellis ; Nikhil Murdeshwar ; Mark A. Eshelman, Semiconductor copper band pad surface protection.
  27. Ellis, Timothy W.; Murdeshwar, Nikhil; Eshelman, Mark A., Semiconductor copper bond pad surface protection.
  28. Ellis, Timothy W.; Murdeshwar, Nikhil; Eshelman, Mark A.; Rheault, Christian, Semiconductor copper bond pad surface protection.
  29. Ellis,Timothy W.; Murdeshwar,Nikhil; Eshelman,Mark A.; Rheault,Christian, Semiconductor copper bond pad surface protection.
  30. Timothy W. Ellis ; Nikhil Murdeshwar ; Mark A. Eshelman ; Christian Rheault, Semiconductor copper bond pad surface protection.
  31. Toyoda, Hiroshi; Nakao, Mitsuhiro; Hasunuma, Masahiko; Kaneko, Hisashi; Sakata, Atsuko; Komukai, Toshiaki, Semiconductor device including an insulating film and insulating pillars and manufacturing method of the semiconductor device.
  32. Toyoda, Hiroshi; Nakao, Mitsuhiro; Hasunuma, Masahiko; Kaneko, Hisashi; Sakata, Atsuko; Komukai, Toshiaki, Semiconductor device with improved bonding.
  33. Yabu Toshiki,JPX ; Segawa Mizuki,JPX, Semiconductor interconnect formed over an insulation and having moisture resistant material.
  34. Yabu, Toshiki; Segawa, Mizuki, Semiconductor interconnect formed over an insulation and having moisture resistant material.
  35. Yabu,Toshiki; Segawa,Mizuki, Semiconductor interconnect formed over an insulation and having moisture resistant material.
  36. Wolf, Kuno; Wallrauch, Alexander; Meinders, Horst; Will, Barbara; Urbach, Peter, Soldering method for mounting electric components.
  37. Jang Syun-Ming,TWX, Top metal and passivation procedures for copper damascene structures.
  38. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang, Wire bond pads.
  39. Daubenspeck,Timothy H.; Gambino,Jeffrey P.; Muzzy,Christopher D.; Sauter,Wolfgang, Wire bond pads.
  40. Besser Paul R. ; Cheung Robin W., Wire bonding CU interconnects.
  41. Chittipeddi, Sailesh; Merchant, Sailesh Mansinh, Wire bonding method for copper interconnects in semiconductor devices.
  42. Lin, Mou-Shiung; Chen, Michael; Chou, Chien-Kang; Chou, Mark, Wirebond pad for semiconductor chip or wafer.
  43. Yamamoto,Hiroshi, Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure.
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