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Mechanism for enabling an array of numerous large high speed counters 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-019/00
출원번호 US-0834119 (1997-04-14)
발명자 / 주소
  • Arimilli Ravi Kumar
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Henkler
인용정보 피인용 횟수 : 21  인용 특허 : 2

초록

A large number of frequent events may be accurately counted by employing a shift register. The values of several bit positions within the shift register are logically combined to generate an input to the shift register. The input is shifted in to alter the register contents whenever an event to be c

대표청구항

[ What is claimed is:] [1.] A method of counting a large number of high speed events, comprising:initializing a fixed width bit pattern;generating an input value from a plurality of bits within said bit pattern; andresponsive to occurrence of a selected event, shifting said input value into said bit

이 특허에 인용된 특허 (2)

  1. Cadieux Kevin (Escondido CA) Hartmann Paul R. (Escondido CA) Pope Kevin (Poway CA), Digital signal comparison circuit in a performance monitoring and test system.
  2. Zandveld Frederik,NLX, Signal generating device including programmable counters and a programmable serial bit pattern generator.

이 특허를 인용한 특허 (21)

  1. Banning, John; Anvin, H. Peter; Bedicheck, Robert; Rozas, Guillermo J.; Shaw, Andrew; Torvalds, Linus; Wilson, Jason, Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version.
  2. Krymski, Alexander I., Fast and accurate adjustment of gain and exposure time for image sensors.
  3. Rozas, Guillermo J.; D'Souza, Godfrey P.; Price, Charles R.; Serris, Paul S., Method and apparatus for enhancing scheduling in an advanced microprocessor.
  4. Rozas, Guillermo J.; D'Souza, Godfrey P.; Price, Charles R.; Serris, Paul S., Method and apparatus for enhancing scheduling in an advanced microprocessor.
  5. Rao Ravi S. ; Garbus Elliot D., Method and apparatus for providing scaled ratio counters to obtain agent profiles.
  6. Bass, Brian Mitchell; Davis, Gordon Taylor; Heddes, Marco C., Method and structure for managing large counter arrays.
  7. Banning, John; Coon, Brett; Torvalds, Linus; Choy, Brian; Wing, Malcolm; Gainer, Patrick, Method and system for storing and retrieving a translation of target program instruction from a host processor using fast look-up of indirect branch destination in a dynamic translation system.
  8. Johnson, Richard; Rozas, Guillermo, Method for increasing the speed of speculative execution.
  9. Johnson, Richard; Rozas, Guillermo, Method for increasing the speed of speculative execution.
  10. Bedichek, Robert; Torvalds, Linus; Keppel, David, Method for integration of interpretation and translation in a microprocessor.
  11. Bedichek, Robert; Torvalds, Linus; Keppel, David, Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts.
  12. Rozas, Guillermo J.; Neilly, Michael R., Multi-threading based on rollback.
  13. Brett Coon ; David Keppel ; Charles R. Price, Programmable event counter system.
  14. Bender, Carl Alfred; Hochschild, Peter Heiner; Misra, Ashutosh; Swetz, Richard, RAM based implementation for scalable, reliable high speed event counters.
  15. Bender, Carl Alfred; Hochschild, Peter Heiner; Misra, Ashutosh; Swetz, Richard, RAM based implementation for scalable, reliable high speed event counters.
  16. Rozas, Guillermo J.; Klaiber, Alexander, Setting a flag bit to defer event handling to a safe point in an instruction stream.
  17. Rozas, Guillermo J.; Klaiber, Alexander, Setting a flag bit to defer event handling to one of multiple safe points in an instruction stream.
  18. Aisaka Tetsuya,JPX, Swallow counter with modulus signal output control.
  19. Bass,Brian Mitchell; Davis,Gordon Taylor; Heddes,Marco C., System and method for delayed increment of a counter.
  20. Bass, Brian Mitchell; Davis, Gordon Taylor; Heddes, Marco C., System for delaying the counting of occurrences of a plurality of events occurring in a processor until the disposition of the event has been determined.
  21. Torvalds, Linus; Keppel, David, System for using rate of exception event generation during execution of translated instructions to control optimization of the translated instructions.
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