초록 ▼

A multiple latency synchronous dynamic random access memory includes separate two and three latency control circuits driven by an input latch circuit. Commands received at the multiple latency synchronous dynamic random access memory are converted to a separate set of command signals clocked through

A multiple latency synchronous dynamic random access memory includes separate two and three latency control circuits driven by an input latch circuit. Commands received at the multiple latency synchronous dynamic random access memory are converted to a separate set of command signals clocked through an input latch circuit by a feedback reset signal, such that commands are pipelined for three latency operation. In response to the command signals, the two latency control circuit produces a set of control signals according to a two latency algorithm. In response to the same command signals, the three latency control circuit independently produces a set of three latency control signals according to a three latency algorithm. In two latency operation, access time for signal development is externally controlled, while in three latency operation access time is internally controlled. In three latency operation, signal development time is determined separately for reads and writes. Also, in three latency operation, data is clocked along a data input path with a write latency. The multiple latency synchronous dynamic random access memory includes a pair of output data paths having different delays, where the data path is selected according to two or three latency operation.

대표청구항 ▼

[ I claim:] [1.] A method of precharging a column of a memory array in a synchronous dynamic random access memory (DRAM), comprising the steps of:(a) selecting between a first or second latency mode for the DRAM by providing a latency mode signal;(b) supplying to the DRAM a clock signal including a

[ I claim:] [1.] A method of precharging a column of a memory array in a synchronous dynamic random access memory (DRAM), comprising the steps of:(a) selecting between a first or second latency mode for the DRAM by providing a latency mode signal;(b) supplying to the DRAM a clock signal including a plurality of clock pulses having leading edges;(c) if the first latency mode is selected:(1) enabling access to the column in response to a first leading edge;(2) internally determining an access time with a latency control circuit; and(3) ending access to the column at the end of the determined access time; and(d) if the second latency mode is selected:(1) inhibiting access to the column in response to the first leading edge for a precharge period; and(2) after the precharge period, enabling access to the column until a second leading edge, immediately following the first leading edge.