[특허]Semiconductor component with multi-level interconnect system and method of manufacture

Semiconductor component with multi-level interconnect system and method of manufacture 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/48 H01L-023/52 H01L-029/40
출원번호	US-0703223 (1996-08-26)
발명자 / 주소	Abercrombie David A. Brownson Rickey S. Cherniawski Michael R.
출원인 / 주소	Motorola, Inc.
인용정보	피인용 횟수 : 32 인용 특허 : 0

초록 ▼

A method of manufacturing a semiconductor component with a multi-level interconnect system includes providing a substrate (11), fabricating a device (12) in the substrate (11), forming an interconnect layer (15) over the substrate (11), depositing a dielectric layer (20) over the interconnect layer (15), depositing a separate interconnect layer (21) over the dielectric layer (20), etching a via (31) in the separate interconnect layer (21) and in the dielectric layer (20), and depositing a different interconnect layer (40) over the separate interconnect layer (21) and in the via (31) wherein the another interconnect layer (40) electrically couples the interconnect layer (15) and the separate interconnect layer (21).

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor component with a multi-level interconnect system comprising:a substrate;a semiconductor device supported by the substrate;a first electrically conductive layer overlying the substrate and electrically coupled to the semiconductor device;a first electrically insulative layer overlying the first electrically conductive layer, the first electrically insulative layer having an opening having a contact width: anda second electrically conductive layer overlying the first electrically insulative layer, a first portion of the second electrically conductive layer located in the opening, the second electrically conductive layer physically connected and electrically coupled to the first electrically conductive layer through the opening in the first electrically insulative layer wherein the second electrically conductive layer has a second portion adjacent to the first portion and adjacent to the opening and wherein the second electrically conductive layer has a third portion adjacent to the second portion and wherein widths of the first, second, and third portions are approximately equal to each other and approximately equal to the contact width.

이 특허를 인용한 특허 (32)

Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
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Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
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Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Chip structure and process for forming the same.
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Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.
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Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.
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Pasch Nicholas F. ; Rakkhit Rajat, Integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level, and process for making same.
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Huang,Tai Chun; Yao,Chih Hsiang; Lin,Yih Hsiung; Bao,Tien I; Chen,Bi Trong; Lu,Yung Cheng, Integration film scheme for copper / low-k interconnect.
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Hill, Rodney L., Metal interconnect structure with a side wall spacer that protects an ARC layer and a bond pad from corrosion and method of forming the metal interconnect structure.
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Choi Kyeong Keun,KRX ; Sim Gyu Cheol,KRX, Metal interconnection structure of semiconductor device.
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Kraft, Jochen; Schatzmayr, Martin; Enichlmair, Hubert, Method for producing structure in chips.
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Schifko James R. ; Oldham Danny R., Method for removal of etch residue immediately after etching a SOG layer.
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Huang-Chung Cheng TW; Wei Kai Hong TW; Fu Gow Tarntair TW, Method of fabricating a field emission device on the sidewalls of holes formed in an insulator layer.
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Trivedi, Jigish D., Method of fabricating a stacked local interconnect structure.
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Trivedi,Jigish D., Method of fabricating stacked local interconnect structure.
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Huang, Jui Tsen, Method of relieving wafer stress.
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Hirasawa Koki,JPX ; Ono Teruo,JPX, Multilayered wiring structure and method of manufacturing the same.
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Nicholas F. Pasch ; Rajat Rakkhit, Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level.
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Jigish D. Trivedi, Stacked local interconnect structure and method of fabricating same.
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Jigish D. Trivedi, Stacked local interconnect structure and method of fabricating same.
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Trivedi, Jigish D., Stacked local interconnect structure and method of fabricating same.
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Trivedi, Jigish D., Stacked local interconnect structure and method of fabricating same.
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Trivedi, Jigish D., Stacked local interconnect structure and method of fabricating same.
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Bold, Thomas, System and apparatus that reduce corrosion of an integrated circuit through its bond pads.
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Hill, Rodney, System and method for preventing metal corrosion on bond pads.
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Bold, Thomas, System and method for reducing corrosion of an integrated circuit through its bond pads.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
상세보기
Lin, Mou-Shiung, Top layers of metal for high performance IC's.
상세보기
Lin, Mou-Shiung, Top layers of metal for high performance IC's.
상세보기
Lin, Mou-Shiung, Top layers of metal for high performance IC's.
상세보기
Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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Semiconductor component with multi-level interconnect system and method of manufacture 원문보기

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Semiconductor component with multi-level interconnect system and method of manufacture 원문보기

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