[특허]Method of making non-volatile memory device having a floating gate with enhanced charge retention

[미국특허] Method of making non-volatile memory device having a floating gate with enhanced charge retention 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/8247
출원번호	US-0393138 (1995-02-21)
발명자 / 주소	Ghneim Said N. Fulford Jr. H. Jim
출원인 / 주소	Advanced Micro Devices, Inc.
대리인 / 주소	Daffer
인용정보	피인용 횟수 : 59 인용 특허 : 19

초록 ▼

A non-volatile memory device is fabricated having enhanced charge retention capability. Enhanced charge retention is achieved upon the floating gate of the non-volatile memory device. The floating gate maybe can configured as a stacked or non-stacked pair of polysilicon conductors. In either instance, negative charge programmed upon the floating gate is retained by reducing the presence of positively charged atoms within dielectrics overlying the floating gate conductor. Moreover, diffusion avenues of the positively charged hydrogen are reduced by maintaining a prevalence of relatively strong bond locations within the overlying dielectric layers. Thus, origination of positively charged atoms, such as hydrogen, from those bonds are substantially prevented by processing the hydrogen-containing dielectrics at relatively low temperatures and further processing any subsequent dielectrics and/or conductors overlying the floating gate at relatively low temperatures. Suitable processing temperatures (dielectric deposition and metal sintering temperatures) are temperatures less than 380.degree. C.

대표청구항 ▼

[ What is claimed is:] [1.] A method for fabricating a memory device having a floating gate, comprising the steps of:providing a semiconductor substrate upon which a tunnel oxide is formed;depositing a floating gate upon said tunnel oxide; andforming at an elevational level above said floating gate a hydrogen-containing dielectric having bonded hydrogen which remains in its bonded location during formation of said hydrogen-containing dielectric and further remains in its bonded location after electrons are injected upon said floating gate.

이 특허에 인용된 특허 (19) 인용/피인용 타임라인 분석

Amin Alaaeldin (Dhahran SAX), Architecture for a flash erase EEPROM memory.
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Arima Hideaki (Hyogo JPX) Okumura Yoshinori (Hyogo JPX) Genjo Hideki (Hyogo JPX) Ogoh Ikuo (Hyogo JPX) Yuzuriha Kohjiroh (Hyogo JPX) Nakashima Yuichi (Hyogo JPX), Electrically programmable non-volatile memory device and manufacturing method thereof.
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Mitchell Allan T. (Garland TX) Riemenschneider Bert R. (Murphy TX), Fabricating a single level merged EEPROM cell having an ONO memory stack substantially spaced from the source region.
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Van Buskirk Michael A. (San Jose CA) Plouse Kevin W. (San Jose CA) Pawletko Joseph G. (Sunnyvale CA) Chang Chi (Redwood City CA) Haddad Sameer S. (San Jose CA) Gutala Ravi P. (Sunnyvale CA), Flash EEPROM array with high endurance.
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Haddad Sameer S. (San Jose CA) Chang Chi (Redwood City CA) Matalvo Antonio (San Francisco CA) Van Buskirk Michael A. (San Jose CA), Flash EEPROM array with negative gate voltage erase operation.
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Kressel Henry (Elizabeth NJ) Hsu Sheng T. (Lawrenceville NJ), Memory array with redundant elements.
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Crotti Pier L. (Landriano ITX), Method for fabricating memory cell matrix having parallel source and drain interconnection metal lines formed on the sub.
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Choi Jeong-hyeok (Seoul KRX) Kim Geon-su (Kyunggi KRX) Sin Yun-seong (Kyunggi KRX), Method of making a nonvolatile semiconductor memory device.
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Sethi Rakesh B. (Campbell CA), Method of making a split floating gate EEPROM cell.
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Yuan Jack H. (Cupertino CA) Harari Eliyahou (Los Gatos CA), Method of making dense flash EEprom semiconductor memory structures.
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Mikata Yuuichi (Yokohama JPX) Usami Toshiro (Yokohama JPX), Method of manufacturing a semiconductor memory device having a floating gate electrode composed of 2-10 silicon grains.
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Sakagami Eiji (Kawasaki JPX), Method of manufacturing semiconductor device by controlling the profile of the density of p-type impurities in the sourc.
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Fukatsu Shigemitsu (Okazaki JPX) Asai Akiyoshi (Nisshin JPX), Method of reducing the trap density of an oxide film for application to fabricating a nonvolatile memory cell.
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Chen Zhizhang (Duluth GA) Rohatgi Ajeet (Marietta GA), Methods for passivating silicon devices at low temperature to achieve low interface state density and low recombination.
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Chang Chi (Redwood City CA), One transistor flash EPROM cell.
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Tsubouchi Kazuo (Sendai JPX) Masu Kazuya (Sendai JPX), Process for non-selectively forming deposition film on a non-electron-donative surface.
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Tang Daniel N. (San Jose CA) Lu Wen-Juei (Sunnyvale CA), Process for self aligning a source region with a field oxide region and a polysilicon gate.
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Takasaki Kanetake (Tokyo JPX) Takagi Mikio (Kawasaki JPX) Koyama Kenji (Yokosuka JPX), UV erasable EPROM with UV transparent silicon oxynitride coating.
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IPC	Description
A	생활필수품
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A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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[미국특허] Method of making non-volatile memory device having a floating gate with enhanced charge retention 원문보기