초록 ▼

A method for simultaneously performing bit serial analog to digital conversion (ADC) for a potentially very large number of signals is described. The method is ideally suited for performing on chip ADC in area image sensors. In one embodiment, to achieve N-bit precision, the method employs a one-bit

A method for simultaneously performing bit serial analog to digital conversion (ADC) for a potentially very large number of signals is described. The method is ideally suited for performing on chip ADC in area image sensors. In one embodiment, to achieve N-bit precision, the method employs a one-bit comparator per channel (or set of multiplexed channels) and an N-bit DAC. To achieve N bits of precision, 2.sup.N -1 comparisons are sequentially performed. Each comparison is performed by first setting the DAC output to the desired value and then simultaneously comparing each of the pixel values to that value. If a pixel value is greater than the DAC output value, its comparator outputs a one, otherwise it outputs a zero. By appropriately choosing the sequence of comparison values, the pixel values are sequentially generated. In another embodiment, the DAC is omitted and a continuous ramp signal is generated for comparison with the analog input.

대표청구항 ▼

[ What is claimed is:] [1.] A circuit comprising:an analog-to-digital (A/D) converter comprising:a first signal generator for generating a first signal having a plurality of levels;a comparator having a first input connected to receive said first signal, said comparator having a second input connect

[ What is claimed is:] [1.] A circuit comprising:an analog-to-digital (A/D) converter comprising:a first signal generator for generating a first signal having a plurality of levels;a comparator having a first input connected to receive said first signal, said comparator having a second input connected to receive an analog input to be converted into a digital value;a binary signal generator for generating a series of binary signals; anda latch having a first input coupled to receive an output of said comparator, said latch having a data input coupled to receive said binary signals, an output of said comparator controlling when said latch provides an output signal corresponding to a signal applied to said data input,wherein said latch provides at least a portion of an N-bit digital code representing said analog input applied to said second input of said comparator.