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Method of optical metrology of unresolved pattern arrays 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01B-011/00
출원번호 US-0643138 (1996-05-02)
발명자 / 주소
  • Ausschnitt Christopher Perry
  • Brunner Timothy Allan
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    DeLio & Peterson LLCPeterson
인용정보 피인용 횟수 : 136  인용 특허 : 9

초록

A process for determining critical dimension bias or overlay error in a substrate formed by a lithographic process initially provides an array of elements on a substrate, the array comprising a plurality of spaced, substantially parallel elements having a length and a width. The sum of the width of

대표청구항

[ Thus, having described the invention, what is claimed is:] [1.] A method of determining bias or overlay error in a substrate formed by a lithographic process comprising the steps of:a) providing an array of elements on a substrate, the array comprising a plurality of spaced, substantially parallel

이 특허에 인용된 특허 (9)

  1. Bass John F. (Sterling Park VA) Saks Nelson (Alexandria VA) Peckerar Martin (Silver Spring MD), Apparatus and method for aligning a mask and wafer in the fabrication of integrated circuits.
  2. Mller Karl-Heinz (Berlin DEX), Apparatus for adjusting a mask with at least one adjustment mark relative to a semi-conductor wafer provided with at lea.
  3. Hirukawa Shigeru (Kashiwa JPX) Magome Nobutaka (Kawasaki JPX) Suwa Kyoichi (Tokyo JPX), Distortion inspecting method for projection optical system.
  4. Nakagawa Masahiro (Yokohama JPX), Light exposure system.
  5. Kikkawa Atsushi (Osaka JPX) Kondo Noriyuki (Kyoto JPX) Tamada Atsushi (Kyoto JPX), Line width measuring device and method.
  6. Brueck Steven R. J. (5601 Cometa Ct. NE. Albuquerque NM 87111) Zaidi Saleem H. (6020 Kathryn SE. ; Apt. #24 Albuquerque NM 87108), Method and apparatus for alignment and overlay of submicron lithographic features.
  7. Ports Kenneth A. (Indialantic FL), Method of measuring misalignment between levels on a substrate.
  8. Tissier Annie (Saint Ismier FRX) Galvier Jean (Saint Martin d\Heres FRX), Process for measuring the dimensions of a spacer.
  9. Yanagisawa Masayuki (Tokyo JPX), Process of manufacturing semiconductor devices.

이 특허를 인용한 특허 (136)

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