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A central processing unit (CPU) in a computer that permits speculative parallel execution of more than one instruction thread. The CPU uses Fork-Suspend instructions that are added to the instruction set of the CPU, and are inserted in a program prior to run-time to delineate potential future thread

A central processing unit (CPU) in a computer that permits speculative parallel execution of more than one instruction thread. The CPU uses Fork-Suspend instructions that are added to the instruction set of the CPU, and are inserted in a program prior to run-time to delineate potential future threads for parallel execution. The CPU has an instruction cache with one or more instruction cache ports, a bank of one or more program counters, a bank of one or more dispatchers, a thread management unit that handles inter-thread communications and discards future threads that violate dependencies, a set of architectural registers common to all threads, and a scheduler that schedules parallel execution of the instructions on one or more functional units in the CPU.

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[ We claim:] [1.] A central processing apparatus in a computer comprising:a. an instruction cache memory having a plurality of instructions, the instruction cache further having one or more instruction cache ports;b. a program counter bank of more than one program counter, each program counter capab

[ We claim:] [1.] A central processing apparatus in a computer comprising:a. an instruction cache memory having a plurality of instructions, the instruction cache further having one or more instruction cache ports;b. a program counter bank of more than one program counter, each program counter capable of independently addressing one or more instructions in the instruction cache, and porting the addressed instructions to one of the instruction cache ports;c. a register file including a fixed set of one or more architected registers;d. a thread management unit, under control of one or more of the instructions, that forks one or more threads, each thread having a sequence of the instructions that is executed by being addressed by one of the program counters, the thread management unit further handling zero or more inter-thread communications, the inter-thread communications capable of communicating controls between one or more pairs of the threads, the controls resolving zero or more inter-thread control dependences between any of the pairs of threads, and the inter-thread communications further capable of communicating data through one or more of the architected registers resolving zero or more inter-thread data dependences between any of the pairs of threads, the register file being accessible by instructions in every thread;e. a dispatcher bank of more than one dispatcher, each dispatcher having an associated instruction buffer and each dispatcher being capable of receiving instructions from one or more of the instruction cache ports, placing the received instruction in the respective associated instruction buffer, decoding the instructions, and performing an intra-thread dependency analysis that analyzes intra-thread dependences among the instructions in the respective associated instruction buffer; andf. a scheduler that receives instructions from all the dispatchers and schedules the instructions for execution on one or more functional units, reby one or more instruction threads are executed by the functional units in parallel.