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Process for forming a semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/00
출원번호 US-0895017 (1997-07-16)
발명자 / 주소
  • Jain Ajay
출원인 / 주소
  • Motorola, Inc.
대리인 / 주소
    Meyer
인용정보 피인용 횟수 : 190  인용 특허 : 3

초록

A process for forming a semiconductor device (68) in which an insulating layer (52) is nitrided and then covered by a thin adhesion layer (58) before depositing a composite copper layer (62). This process does not require a separate diffusion barrier as a portion of the insulating layer (52) has bee

대표청구항

[ I claim:] [1.] A process for forming a semiconductor device comprising the steps of:forming a patterned insulating layer over a substrate, wherein the patterned insulating layer includes an opening;converting a portion of the patterned insulating layer to a barrier film;depositing an adhesion laye

이 특허에 인용된 특허 (3)

  1. Cadien Kenneth C. (Portland OR) Sivaram Srinivasam (San Jose CA), Integrated tungsten/tungsten silicide plug process.
  2. Jain Ajay ; Lucas Kevin, Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC).
  3. Kinoshita Takao (Fukuyama JPX) Saito Satoshi (Fukuyama JPX), Method of forming a contact.

이 특허를 인용한 특허 (190)

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  7. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  8. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  9. Ahn, Kie Y; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  10. Ahn,Kie Y; Forbes,Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  11. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using enhanced reflow.
  12. Cheung David ; Yau Wai-Fan ; Mandal Robert R., CVD plasma assisted low dielectric constant films.
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  48. Farrar, Paul A., Integrated circuit and seed layers.
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  63. Huang Yimin,TWX, Method for fabricating dual damascene.
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  65. Shih Tsu,TWX ; Chen Ying-Ho,TWX ; Twu Jih-Churng,TWX ; Jang Syun-Ming,TWX, Method for forming a self-aligned copper structure with improved planarity.
  66. Braeckelmann Gregor ; Venkatraman Ramnath ; Herrick Matthew Thomas ; Simpson Cindy R. ; Fiordalice Robert W. ; Denning Dean J. ; Jain Ajay ; Capasso Cristiano, Method for forming a semiconductor device.
  67. Meng-Chang Liu TW; Yuan-Lung Liu TW, Method for forming a top interconnection level and bonding pads on an integrated circuit chip.
  68. Tsai Ming-Hsing,TWX ; Tsai Wen-Jye,TWX ; Shue Shau-Lin,TWX ; Yu Chen-Hua,TWX, Method for improvement of gap filling capability of electrochemical deposition of copper.
  69. Syun-Ming Jang TW, Method for improvement of planarity of electroplated copper.
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  75. Loboda, Mark Jon; Seifferly, Jeffrey Alan, Method for producing hydrogenated silicon oxycarbide films having low dielectric constant.
  76. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX ; Bao Tien-I,TWX ; Jang Syun-Ming,TWX, Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby.
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  87. Xu, Ping; Xia, Li-Qun; Dworkin, Larry A.; Naik, Mehul, Method of eliminating photoresist poisoning in damascene applications.
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  90. Yuasa Hiroshi,JPX ; Ueda Satoshi,JPX, Method of fabricating interconnects utilizing fluorine doped insulators and barrier layers.
  91. Hsu Chen-Chung,TWX ; Chang Yih-Jau,TWX, Method of fabricating semiconductor device for preventing antenna effect.
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  95. Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.
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  97. Buynoski Matthew S. ; Lin Ming-Ren, Method of forming multiple levels of patterned metallization.
  98. Suzuki, Mieko; Kubo, Akira, Method of forming polish stop by plasma treatment for interconnection.
  99. Lopatin, Sergey D.; Besser, Paul R.; Buynoski, Matthew S., Method of implantation after copper seed deposition.
  100. Besser, Paul R.; Buynoski, Matthew S.; Lopatin, Sergey D., Method of implanting copper barrier material to improve electrical performance.
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  102. Chan Lap ; Zheng Jia Zhen,SGX, Method of making a copper interconnect with top barrier layer.
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