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Semiconductor die carrier having a dielectric epoxy between adjacent leads 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
출원번호 US-0902032 (1997-07-29)
발명자 / 주소
  • Mosley Joseph M.
  • Portuondo Maria M.
출원인 / 주소
  • The Panda Project
대리인 / 주소
    Morgan, Lewis & Bockius LLP
인용정보 피인용 횟수 : 188  인용 특허 : 54

초록

A semiconductor die carrier includes an insulative module; a plurality of electrically conductive leads extending from the insulative module; a semiconductor die housed with the insulative module; and at least one high frequency capacitor secured to the insulative module for facilitating transmissio

대표청구항

[ What is claimed is:] [1.] A semiconductor die carrier comprising:a module for housing a semiconductor die, said module comprising a top, a bottom, and a plurality of planar outer side surfaces;a row of electrically conductive leads extending from at least one of said outer side surfaces of the mod

이 특허에 인용된 특허 (54)

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  33. Martens John D. (Plano TX) Ammon J. Preston (Dallas TX), Multi row high density connector.
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  43. Sakemi Shouzi (Fukuoka JPX) Sakai Tadahiko (Fukuoka JPX), Printed circuit board.
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  132. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  133. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  134. Lee, Sun Goo; Jang, Sang Jae; Lee, Choon Heung; Yoshida, Akito, Semiconductor package capable of die stacking.
  135. Lee, Sun Goo; Lee, Choon Heung; Lee, Sang Ho, Semiconductor package exhibiting efficient lead placement.
  136. Jang, Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
  137. Jang,Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
  138. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
  139. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
  140. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
  141. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
  142. Paek,Jong Sik, Semiconductor package including flip chip.
  143. Lee,Seung Ju; Do,Won Chul; Lee,Kwang Eung, Semiconductor package including leads and conductive posts for providing increased functionality.
  144. Yang, Jun Young; Lee, Sun Goo; Lee, Choon Heung, Semiconductor package including low temperature co-fired ceramic substrate.
  145. Yang,Sung Jin; Ha,Sun Ho; Kim,Ki Ho; Son,Sun Jin, Semiconductor package with chamfered corners and method of manufacturing the same.
  146. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
  147. St. Amand, Roger D.; Perelman, Vladimir, Semiconductor package with fast power-up cycle and method of making same.
  148. Lee, Chang Deok; Na, Do Hyun, Semiconductor package with half-etched locking features.
  149. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making same.
  150. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making the same.
  151. Lee, Choon Heung; Foster, Donald C.; Choi, Jeoung Kyu; Kim, Wan Jong; Youn, Kyong Hoon; Lee, Sang Ho; Lee, Sun Goo, Semiconductor package with increased number of input and output pins.
  152. Lee,Choon Heung; Foster,Donald C.; Choi,Jeoung Kyu; Kim,Wan Jong; Youn,Kyong Hoon; Lee,Sang Ho; Lee,Sun Goo, Semiconductor package with increased number of input and output pins.
  153. Kim, Do Hyeong; Kim, Bong Chan; Kim, Yoon Joo; Chung, Ji Young, Semiconductor package with patterning layer and method of making same.
  154. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
  155. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
  156. Alvarez, Robert; Moehle, Paul R.; Kellher, Harold T., Stabilizer/spacer for semiconductor device.
  157. Crowley,Sean Timothy; Alvarez,Angel Orabuena; Yang,Jun Young, Stackable semiconductor package and method for manufacturing same.
  158. Yang, Jun Young, Stackable semiconductor package and method for manufacturing same.
  159. Heo, Byong II, Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same.
  160. Scanlan, Christopher M.; Berry, Christopher J., Stackable semiconductor package including laminate interposer.
  161. Huemoeller,Ronald Patrick; Rusli,Sukianto; Hiner,David Jon, Stacked embedded leadframe.
  162. Kim, Yoon Joo; Kim, In Tae; Chung, Ji Young; Kim, Bong Chan; Kim, Do Hyung; Ha, Sung Chul; Lee, Sung Min; Song, Jae Kyu, Stacked semiconductor package and method of making same.
  163. Grundy,Kevin P.; Wiedemann,William F.; Fjelstad,Joseph C., Stair step printed circuit board structures for high speed signal transmissions.
  164. Keith W. Goossen, System and method of transmission using coplanar bond wires.
  165. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
  166. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
  167. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.
  168. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
  169. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
  170. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  171. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  172. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  173. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  174. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  175. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  176. Huemoeller, Ronald Patrick; Lie, Russ; Hiner, David, Two-sided fan-out wafer escape package.
  177. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
  178. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
  179. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  180. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  181. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  182. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  183. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  184. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  185. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  186. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  187. Huemoeller,Ronald Patrick; Rusli,Sukianto; Razu,David, Wafer level package and fabrication method.
  188. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package fabrication method.
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