초록 ▼

A network controller, which allows data frames received to be held in an internal memory buffer, has the capability to selectively switch between a DMA mode of data transfer and a non-DMA mode of data transfer to move data frames from the internal memory buffer to a desired location. When the overfl

A network controller, which allows data frames received to be held in an internal memory buffer, has the capability to selectively switch between a DMA mode of data transfer and a non-DMA mode of data transfer to move data frames from the internal memory buffer to a desired location. When the overflow of the memory buffer is anticipated, a DMA controller is automatically engaged to move the data frames to a system memory to prevent the received frames from being discarded. An auto-DMA decision logic engages the DMA controller based on factors such as the number of data frames accumulated in the memory buffer, remaining capacity of the memory buffer, frame loading and unloading rates, and time interval during which data frames have been received without completely unloading the memory buffer.

대표청구항 ▼

[ I claim:] [1.] A system for loading and unloading data frames each including a predetermined plurality of words, comprising:an interface controller for handling data frames from a data frame source;a memory buffer for storing data frames handled by said interface controller;a system memory having

[ I claim:] [1.] A system for loading and unloading data frames each including a predetermined plurality of words, comprising:an interface controller for handling data frames from a data frame source;a memory buffer for storing data frames handled by said interface controller;a system memory having a capacity larger than said memory buffer for storing data frames from said memory buffer; anda DMA controller responsive to said interface controller, for transferring data frames from said memory buffer to said system memory;wherein said interface controller further comprises:a frame start and frame end detector (FS/FED) for detecting the beginning and end of each data frame handled by said interface controller for storage in said memory buffer;a buffer manager for monitoring the quantity of data frames supplied to said memory buffer and receiving the addresses of first and last words of data frames stored in said memory buffer at respective first and second detection times when said FS/FED respectively detects the first and last words of a frame; anda switch responsive to said buffer manager for automatically engaging said DMA controller when said buffer manager monitors excessive data frames stored in said memory buffer.