초록 ▼

An apparatus for protecting an integrated circuit against damage from electrostatic discharge (ESD) includes an ESD bus that is connected to multiple input pads through a respective diode. The ESD bus--the node to be protected--is coupled to the negative power supply bus (V.sub.ss) by a FET-triggere

An apparatus for protecting an integrated circuit against damage from electrostatic discharge (ESD) includes an ESD bus that is connected to multiple input pads through a respective diode. The ESD bus--the node to be protected--is coupled to the negative power supply bus (V.sub.ss) by a FET-triggered SCR circuit. In particular, the SCR circuit includes, equivalently, a PNP bipolar transistor, and an NPN bipolar transistor interconnected so that each transistor receives base current from the collector terminal of the other. A field effect transistor (FET) is configured to trigger the SCR into conduction, to thereby provide a low-impedance path to safely shunt ESD charge. The drain terminal of the FET is connected to an intermediate node of a resistance between the ESD bus, and the PNP emitter terminal. ESD charge on an input pad of the integrated circuit forward biases the respective diodes, and charges the ESD bus. When the voltage on the ESD bus reaches a predetermined threshold voltage, the FET drain region breaks down, and triggers the SCR circuit into conduction to shunt the charge on the ESD bus to V.sub.ss. The voltage drop occasioned by current flowing from the ESD bus to the intermediate node at the onset of the FET drain breakdown hastens the turn-on of the SCR, thus improving the response time for handling fast ESD events, such as those in accordance with the Charged Device Model (CDM).

대표청구항 ▼

[ I claim:] [1.] An apparatus for protecting a semiconductor device from excessive charge, the device including an interface pad selected from the group including an input pad, an output pad, and an input/output pad, comprising:an SCR circuit configured to transfer charge from an electrostatic disch

[ I claim:] [1.] An apparatus for protecting a semiconductor device from excessive charge, the device including an interface pad selected from the group including an input pad, an output pad, and an input/output pad, comprising:an SCR circuit configured to transfer charge from an electrostatic discharge (ESD) bus to a negative bus of a power supply;a field effect transistor (FET) coupled to said SCR circuit;a first impedance element connected between the ESD bus and a common node;a second impedance element connected between the common node and said SCR circuit; anda first diode for coupling said interface pad to said ESD bus, said first diode having an anode and a cathode, wherein said interface pad is connected to said anode;said FET being further coupled to said common node and configured to activate transfer of charge by said SCR circuit when a voltage on the ESD bus reaches a predetermined threshold level.