초록 ▼

A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely

A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

대표청구항 ▼

[ I claim:] [1.] A semiconductor memory device provided for operation with a plurality of cell-refreshing sense-amplifiers (SAs) comprising:a memory cell array having a plurality of first-direction first-level bit lines disposed in a parallel manner along a first direction;said memory cell array fur

[ I claim:] [1.] A semiconductor memory device provided for operation with a plurality of cell-refreshing sense-amplifiers (SAs) comprising:a memory cell array having a plurality of first-direction first-level bit lines disposed in a parallel manner along a first direction;said memory cell array further includes a plurality of word lines intersected with said first-direction first-level bit lines;said memory cell array further includes a plurality of memory cells wherein each of said plurality of memory cells being coupled between one of said first-direction first level bit lines and one of said word lines for storing data therein;a plurality of different-direction first level bit lines disposed along a plurality of different directions with at least one of said different directions being different from said first direction, wherein each of said first direction first level bit lines connected to one of said cell-refreshing sense amplifiers (SAs) directly or via said different-direction first level bit-lines;a decoder for generating an activating signal for activating one of said word lines wherein said decoder further includes a plurality of drain select lines each being provided for receiving one of a plurality of mutual exclusively drain select signals;said decoder further includes a plurality of gate select lines each being provided for receiving one of a plurality of mutual exclusively gate select signals;said decoder further includes a plurality of transistors wherein each transistor includes a drain which being connected correspondingly to one of said plurality of drain select input lines for receiving one of said mutually exclusive drain select signals therefrom;each of said transistors further includes a gate which being connected correspondingly to one of said plurality of gate select input lines for receiving one of said mutually exclusive gate select signals therefrom; andeach of said plurality of transistors further includes a source which is connected to an output signal line for providing said activating signal which being contingent upon said mutually exclusive drain select signals and said mutually exclusive gate select signals.