초록 ▼

The performance of a computer system which use reduction of clock speed to conserve power is enhanced by dynamically adjusting the minimum number of clock cycles required for memory access ("wait states"). When the computer system decreases its clock speed, the minimum number of wait states is decre

The performance of a computer system which use reduction of clock speed to conserve power is enhanced by dynamically adjusting the minimum number of clock cycles required for memory access ("wait states"). When the computer system decreases its clock speed, the minimum number of wait states is decreased to account for the longer cycle time. Likewise, when the computer system increases its clock speed, this invention determines whether any increase in the minimum number of wait states is required, and if so, implements such an increase.

대표청구항 ▼

[ What is claimed is:] [2.] A method of improving performance in a power-managed computer system having a minimum number of memory access wait states, the method comprising the steps of:(a) detecting a request to change a clock speed of said system;(b) determining if implementation of said request r

[ What is claimed is:] [2.] A method of improving performance in a power-managed computer system having a minimum number of memory access wait states, the method comprising the steps of:(a) detecting a request to change a clock speed of said system;(b) determining if implementation of said request requires a decrease in said clock speed; and(c) implementing said request; and(d) adjusting the minimum number of memory access wait states based on said request.