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Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0959106 (1997-10-23)
발명자 / 주소
  • Bandyopadhyay Basab
  • Fulford
  • Jr. H. Jim
  • Dawson Robert
  • Hause Fred N.
  • Michael Mark W.
  • Brennan William S.
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Daffer
인용정보 피인용 횟수 : 73  인용 특허 : 0

초록 ▼

A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal pla

대표청구항 ▼

[ What is claimed is:] [1.] A method for forming a multilevel interconnect structure, comprising:forming at least two first conductors spaced across a semiconductor topography;depositing a first dielectric upon said first conductors;forming an etch stop upon a portion of said first dielectric;deposi

이 특허를 인용한 특허 (73)

  1. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
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  2. Lytle,Steven A., Dual damascene process with no passing metal features.
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  3. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
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  4. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
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  5. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
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  6. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
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  7. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
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  8. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Integrated circuit having conductors of enhanced cross-sectional area.
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  9. Shue, Shau-Lin; Tsai, Ming-Hsin, Method for integrating low-K materials in semiconductor fabrication.
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  10. Shue, Shau-Lin; Tsai, Ming-Hsing, Method for integrating low-K materials in semiconductor fabrication.
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  11. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
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  12. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
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  13. Ma Kin F. ; Stubbs Eric T., Method for reducing capactive coupling between conductive lines.
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  14. Yew Tri-Rung,TWX ; Lur Water,TWX ; Sun Shih-Wei,TWX, Method for unlanded via etching using etch stop.
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  15. Cronin John E. ; Luther Barbara J., Method of fabricating a stacked via in copper/polyimide beol.
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  17. Lee, John K.; Kim, Hyuntae; Stocks, Richard L.; Tran, Luan, Methods for fabricating contacts of semiconductor device structures and methods for designing semiconductor device structures.
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  18. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
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  19. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  20. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  21. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  22. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  23. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  24. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  25. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
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  26. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
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  27. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
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  28. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
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  29. Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S., Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof.
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  30. Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S., Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof.
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  31. Miyamoto, Koji; Yoshida, Kenji; Kaneko, Hisashi, Semiconductor integrated circuit device having multilevel interconnection.
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  32. Miyamoto, Koji; Yoshida, Kenji; Kaneko, Hisashi, Semiconductor integrated circuit device having multilevel interconnection.
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  33. Cronin, John E.; Luther, Barbara J., Stacked via in copper/polyimide BEOL.
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  34. Cappola, Kenneth, Surgical instrument.
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  35. Cappola, Kenneth, Surgical instrument.
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  37. Cappola, Kenneth, Surgical instrument.
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  38. Cappola, Kenneth M., Surgical instrument.
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  39. Marczyk, Stanislaw; Cappola, Kenneth; Maffei, Frank C., Surgical stapling apparatus.
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  40. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  41. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  48. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  49. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  50. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  51. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  52. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  57. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  58. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  60. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  63. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  64. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  65. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  66. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  67. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  69. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  70. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  71. Mou-Shiung Lin TW, Top layers of metal for high performance IC's.
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  72. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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  73. Chow, David GenLong, Transmission line structure and method of signal propagation.
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