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Function unit for fine-gained FPGA 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0708134 (1996-08-27)
우선권정보 GB-0023226 (1992-11-05)
발명자 / 주소
  • Kean Thomas A.,GB6
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Young
인용정보 피인용 횟수 : 115  인용 특허 : 25

초록 ▼

An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowin

대표청구항 ▼

[ I claim:] [1.] A function unit comprising:a plurality of multiplexers; andat least one flip-flop,wherein a first set of said plurality of multiplexers receive input signals from a hierarchical interconnect system, and a second second set of said plurality of multiplexers receive output signals and

이 특허에 인용된 특허 (25)

  1. Hofmann Ruediger (Gilching DEX), Broad band signal switching matrix.
    상세보기
  2. Trumpp Gerhard (Puchheim DEX) Wolkenhauer Jan (Munich DEX), Broadband signal switching matrix network.
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  3. Waller William K. (Boise ID), Compact multifunction logic circuit.
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  4. Kean Thomas A. (Edinburgh GB6), Configurable cellular array.
    상세보기
  5. Freeman Ross H. (San Jose CA), Configurable electrical circuit having configurable logic elements and configurable interconnects.
    상세보기
  6. Carter William S. (Santa Clara CA), Configurable logic element.
    상세보기
  7. Lin Wen-Tai (Schenectady NY) Hwang Jyh-Pin (Schenectady NY), Crossbar switch with distributed memory.
    상세보기
  8. Ho Walford W. (Saratoga CA) Chen Chao-Chiang (Cupertino CA) Yang Yuk Y. (Foster City CA), Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array.
    상세보기
  9. Freeman Ross H. (San Jose CA), Integrated circuit programmable cross-point connection technique.
    상세보기
  10. Sutherland Jim (Sunnyvale CA), Local and express diagonal busses in a configurable logic array.
    상세보기
  11. Reed Paul A. (Austin TX), Memory system for reliably writing addresses with reduced power consumption.
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  12. Chan Yiu-Fai (Saratoga CA) Hung Chuan-Yung (Cupertino CA), Method and apparatus for programming and verifying programmable elements in programmable devices.
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  13. Carter William S. (Santa Clara CA), Microprocessor oriented configurable logic element.
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  14. Veenstra Kerry (San Jose CA), Multiplexer structures for use in making controllable interconnections in integrated circuits..
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  15. Hillis W. Daniel (Cambridge MA), Partitioning the processors of a massively parallel single array processor into sub-arrays selectively controlled by hos.
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  16. Chan Andrew K. (Palo Alto CA) Birkner John M. (Portola Valley CA) Chua Hua-Thye (Los Alto Hills CA), Programmable application specific integrated circuit and logic cell therefor.
    상세보기
  17. Stockton David W. (Palm Bay FL), Programmable chip enable logic function.
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  18. Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array.
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  19. Sakamoto Makoto (Chiba JPX), Programmable logic device having programmable wiring for connecting adjacent programmable logic elements through a singl.
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  20. ElAyat Khaled A. (Cupertino CA) Bakker Gregory W. (Sunnyvale CA) Lien Jung-Cheun (San Jose CA) Plants William C. (Santa Clara CA) Kaptanoglu Sinan (San Carlos CA) Gopisetty Runip (Los Gatos CA) Chan , Programmable logic module and architecture for field programmable gate array device.
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  21. El Gamal Abbas (Palo Alto CA) Chiang Steve S. S. (Saratoga CA), Reconfigurable programmable interconnect architecture.
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  22. Greene Johathan W. (Palo Alto CA) El Gamal Abbas A. (Palo Alto CA) Kaptanoglu Sinan (San Carlos CA), Segmented routing architecture.
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  23. Iwai Hidetoshi (Fucyu JPX) Miyazawa Kazuyuki (Kodaira JPX), Semiconductor storage device with redundancy arrangement.
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  24. Elgamal Abbas (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Mohsen Amr (Saratoga CA), User programmable integrated circuit interconnect architecture and test method.
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  25. Nederlof Leendert (Eindhoven CA NLX) Salters Roelof H. W. (Sunnyvale CA), Word-organized, content-addressable memory.
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