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[미국특허] Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction c 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0592089 (1996-01-26)
발명자 / 주소
  • Whittaker Bruce Ernest
출원인 / 주소
  • Unisys Corporation
대리인 / 주소
    Kozak
인용정보 피인용 횟수 : 128  인용 특허 : 8

초록 ▼

A multi-set cache structure, providing a first-level cache and second level cache to a processor, stores data words where each word holds two bytes and two status bits. Each cache set includes a Tag RAM for holding the address data words and a Parity RAM holding a parity bit for each byte and a pari

대표청구항 ▼

[ What is claimed is:] [1.] In a computer network having a multi-set cache structure which includes a small first level cache and a large second level cache supporting a central processor, said second level cache providing a set of Tag RAMs holding address words of two bytes each with two status bit

이 특허에 인용된 특허 (8) 인용/피인용 타임라인 분석

  1. Nadir James (San Jose CA) Chu Ching-Hua (San Jose CA), Circuit and method for selecting a set in a set associative cache.
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  2. Tsuchiya Kenichi (New Brighton MN), Failure detection for instruction processor associative cache memories.
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  3. Tipley Roger E. (Houston TX), Method and apparatus for achieving multilevel inclusion in multilevel cache hierarchies.
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  4. Nadir James (San Jose CA) Chu Ching-Hua (San Jose CA), Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking.
    상세보기
  5. Hassoun Soha M. N. (Worcester MA) Sanders Douglas E. (Framingham MA), Method and apparatus for parity generation.
    상세보기
  6. Shen Ju (San Jose) Chan Albert L. (Palo Alto) Shankar Kapil (San Jose CA) Tsui Cyrus (Vancouver WA), Output logic macrocell with enhanced functional capabilities.
    상세보기
  7. So Kimming (Austin TX) Wang Wen-Hann (Portland OR), System and method for practicing essential inclusion in a multiprocessor and cache hierarchy.
    상세보기
  8. Metzger Jeffrey A. (Leominster MA) Maskas Barry A. (Sterling MA), Update vs. invalidate policy for a snoopy bus protocol.
    상세보기

이 특허를 인용한 특허 (128) 인용/피인용 타임라인 분석

  1. Larson, Douglas A.; Cronin, Jeffrey J, Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
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  2. Larson, Douglas A.; Cronin, Jeffrey J., Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
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  3. Larson, Douglas A.; Cronin, Jeffrey J., Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
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  4. Larson, Douglas A.; Cronin, Jeffrey J., Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
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  5. Jeddeloh, Joseph M., Apparatus and method for direct memory access in a hub-based memory system.
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  6. Jeddeloh,Joseph M., Apparatus and method for direct memory access in a hub-based memory system.
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  7. Jeddeloh,Joseph M., Apparatus and method for direct memory access in a hub-based memory system.
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  8. Radke,William; Peterson,James R., Apparatus and method for distributed memory control in a graphics processing system.
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  63. Weiberle, Reinhard; Mueller, Bernd; Kottke, Thomas, Method and device for error detection for a cache memory and corresponding cache memory.
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  66. Jeddeloh, Joseph M.; Lee, Terry R., Method and system for controlling memory accesses to memory modules having a memory hub architecture.
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  67. Jeddeloh,Joseph M.; Lee,Terry R., Method and system for controlling memory accesses to memory modules having a memory hub architecture.
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  68. James, Ralph, Method and system for synchronizing communications links in a hub-based memory system.
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  69. James,Ralph, Method and system for synchronizing communications links in a hub-based memory system.
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  80. Jeddeloh,Joseph M.; Lee,Terry R., Posted write buffers and methods of posting write requests in memory modules.
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  81. Lee, Terry R.; Jeddeloh, Joseph M., Reconfigurable memory module and method.
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  82. Lee, Terry R.; Jeddeloh, Joseph M., Reconfigurable memory module and method.
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