초록 ▼

An instruction fetch and issuance unit (200) fetches two instruction words and issues at least one instruction word to an instruction decoder (250) per clock cycle. Two multiplexers (220, 230) receive the two fetched instructions and one or both of two of three words stored in an instruction registe

An instruction fetch and issuance unit (200) fetches two instruction words and issues at least one instruction word to an instruction decoder (250) per clock cycle. Two multiplexers (220, 230) receive the two fetched instructions and one or both of two of three words stored in an instruction register (240). A controller (210) selectively controls (207-209), in accordance with a state diagram (300), the loading of three words into the instruction register (240) from among the inputs of the multiplexers (220,230). The instruction register (240) issues up to two instructions per clock cycle without requiring the processor to stall to retrieve an additional word, allowing efficient issuance of a double-word instruction or two instructions in parallel.

대표청구항 ▼

[ What is claimed is:] [1.] An instruction fetch and issue apparatus for a data processing system having an instruction set including multiple word instructions or that issues multiple instructions in parallel, comprising:an instruction register having a first register, a second register, and a thir

[ What is claimed is:] [1.] An instruction fetch and issue apparatus for a data processing system having an instruction set including multiple word instructions or that issues multiple instructions in parallel, comprising:an instruction register having a first register, a second register, and a third register containing a first register word, a second register word and a third register word, respectively, wherein the instruction register transfers instruction words from the first register, second register, and third register, in response to a load signal;a first multiplexer that receives a first instruction word and a second instruction word from a memory and receives the second and third register words from the instruction register, and transfers a selected one of the received words into the first register in the instruction register based on a first control signal; anda second multiplexer that receives the first and second instruction words from the memory and the third register word, and transfers a selected one of the received words into the second register based on a second control signal.