초록 ▼

A circuit for protecting a bonding pad of a semiconductor device from ESD voltages is located under the pad to permit the space otherwise used for a protection circuit to be used for normal operating components. The protection circuit has a compact layout that provides maximum ability to handle an E

A circuit for protecting a bonding pad of a semiconductor device from ESD voltages is located under the pad to permit the space otherwise used for a protection circuit to be used for normal operating components. The protection circuit has a compact layout that provides maximum ability to handle an ESD current within this limited space. The semiconductor structure for the circuit has separate parts for two SCR circuits, one for each polarity of ESD current. Each SCR circuit comprises two symmetrical SCR structures.

대표청구항 ▼

[ I claim:] [1.] In a semiconductor device of a type having a substrate, a first bonding pad for making an external connection to the semiconductor device, a pad metal structure underlying the first bonding pad and extending on a surface of the semiconductor device to circuits that may be damaged by

[ I claim:] [1.] In a semiconductor device of a type having a substrate, a first bonding pad for making an external connection to the semiconductor device, a pad metal structure underlying the first bonding pad and extending on a surface of the semiconductor device to circuits that may be damaged by an ESD voltage at the first bonding pad, and other bonding pads for connection to two power supply terminals,an improved protective device for conducting ESD voltages to the power supply terminals, comprising:a first SCR circuit comprising first and second wells formed in the substrate and spaced apart and underlying at least part of the first bonding pad;means connecting the pad metal structure to the first well, and means forming a connection to the substrate and establishing a resistive path through the substrate between one of the power supply terminals and the circuits that may be damaged; andan N+ diffusion region formed in the second well and forming an emitter of a vertical NPN parasitic bipolar transistor constituting part of the first SCR circuit,the first well forming an emitter of a lateral PNP parasitic bipolar transistor,an intervening portion of the substrate forming a base of the PNP transistor and the substrate underlying the second well forming a collector of the NPN transistor,the second well forming a base of the NPN transistor and a collector of the PNP transistor,whereby the PNP and NPN transistors form the first SCR circuit with a vertical path through the second well forming a collector resistor of the PNP transistor and a path through the first well forming a resistor in an emitter circuit of the PNP transistor.