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MOS semiconductor device with excellent drain current 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
  • H01L-029/94
  • H01L-031/062
  • H01L-031/113
출원번호 US-0664957 (1996-06-13)
우선권정보 JP-0150112 (1995-06-16)
발명자 / 주소
  • Yamashita Kyoji,JPX
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd., JPX
대리인 / 주소
    Ratner & Prestia
인용정보 피인용 횟수 : 42  인용 특허 : 0

초록

A MOS semiconductor device includes a first conductivity type silicon layer having a main surface; a gate insulating film selectively formed on the main surface of the silicon layer; a gate electrode provided on the gate insulating film; an insulating side wall formed on the side of the gate electro

대표청구항

[ What is claimed is:] [1.] A MOS semiconductor device, comprising:a first conductivity type silicon layer having a main surface;a gate insulating film selectively formed on said main surface of said silicon layer;a gate electrode provided on the gate insulating film;an insulating side wall formed o

이 특허를 인용한 특허 (42)

  1. Chan, Kevin K.; Lavoie, Christian; Rim, Kern, MOSFET structure with multiple self-aligned silicide contacts.
  2. Chan, Kevin K.; Lavoie, Christian; Rim, Kern, MOSFET structure with multiple self-aligned silicide contacts.
  3. Chan,Kevin K.; Lavoie,Christian; Rim,Kern, MOSFET structure with multiple self-aligned silicide contacts.
  4. Wu Shye-Lin,TWX, MOSFETS structure with a recessed self-aligned silicide contact and an extended source/drain junction.
  5. Lee, Hi Deok, Method for fabricating semiconductor device.
  6. Oda Noriaki,JPX, Method for producing semiconductor device.
  7. Thomas Michael E. ; Daniels Brian J., Method for silicide stringer removal in the fabrication of semiconductor integrated circuits.
  8. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  9. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  10. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  11. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  12. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  13. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  14. French Ian D.,GBX ; Powell Martin J.,GBX, Method of fabricating a thin film transistor.
  15. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  16. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  17. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  18. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  19. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  20. Yamazaki, Shunpei, Method of manufacturing a semiconductor device having a gate electrode formed over a silicon oxide insulating layer.
  21. Yamazaki, Shunpei, Method of manufacturing a semiconductor device including thermal oxidation to form an insulating film.
  22. Yamazaki, Shunpei, Method of manufacturing semiconductor device having island-like single crystal semiconductor layer.
  23. Tsai, Teng-Chun; Lin, Cheng-Tung; Wang, Li-Ting; Chen, De-Fang; Lin, Huan-Just, Methods for fabricating vertical-gate-all-around transistor structures.
  24. Kim,Duk Soo, Methods of manufacturing semiconductor devices.
  25. Yamazaki, Shunpei; Ohtani, Hisashi; Koyama, Jun; Fukunaga, Takeshi, Nonvolatile memory and electronic apparatus.
  26. Fukunaga, Takeshi, Process for production of SOI substrate and process for production of semiconductor device.
  27. Fukunaga, Takeshi, Process for production of SOI substrate and process for production of semiconductor device including the selective forming of porous layer.
  28. Hsieh Kevin,TWX ; Huang Michael W C,TWX ; Hsieh Wen-Yi,TWX, Self-aligned silicide process.
  29. Yamazaki, Shunpei, Semiconductor device.
  30. Yamazaki, Shunpei; Ohtani, Hisashi; Koyama, Jun; Fukunaga, Takeshi, Semiconductor device having buried oxide film.
  31. Wieczorek Karsen ; Hause Frederick N., Semiconductor device having elevated silicidation layer and process for fabrication thereof.
  32. Igarashi Motoshige,JPX ; Amishiro Hiroyuki,JPX ; Higashitani Keiichi,JPX, Semiconductor device with gate electrode portion and method of manufacturing the same.
  33. Thomas Michael E., Semiconductor device with self aligned contacts having integrated silicide stringer removal and method thereof.
  34. Yamazaki, Shunpei; Koyama, Jun; Miyanaga, Akiharu; Fukunaga, Takeshi, Semiconductor thin film and method of manufacturing the same and semiconductor device and method of manufacturing the same.
  35. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.
  36. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.
  37. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.
  38. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.
  39. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.
  40. Murthy,Anand; Chau,Robert S.; Ghani,Tahir, Semiconductor transistor having a stressed channel.
  41. Suguro, Kyoichi, Sputtering target and method of manufacturing a semiconductor device.
  42. Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Thin film semiconductor device and its manufacturing method.
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