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[미국특허] Method and apparatus for dispatching lots in a factory 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-019/00
  • G06G-007/66
출원번호 US-0859952 (1997-05-21)
발명자 / 주소
  • Yang Terry H.,TWX
  • Chu Harry L.,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Co., Ltd., TWX
대리인 / 주소
    Christensen, O'Connor, Johnson & Kindness PLLC
인용정보 피인용 횟수 : 47  인용 특허 : 0

초록

A lot dispatching method and apparatus for dispatching WIP lots in the manufacture of semiconductor integrated circuits includes determining an average process time (T) and average number of lots per batch (a) of a succeeding process, and determining allowable lots (k) of a preceding process. The al

대표청구항

[ What is claimed is:] [20.] Apparatus for dispatching work in process (WIP) lots in a factory, said apparatus comprising:a succeeding tool configured to perform a succeeding process on a batch of lots, the succeeding tool having a maximum batch size B, an average process time T and an average batch

이 특허를 인용한 특허 (47) 인용/피인용 타임라인 분석

  1. Wegerich,Stephan W.; Bell,David R.; Xu,Xiao, Adaptive modeling of changed states in predictive condition monitoring.
  2. Lin, Ta-Chin; Huang, Yi-Feng; Lai, Fu-Kang; Hsiao, Jen-Chih, Algorithms tunning for dynamic lot dispatching in wafer and chip probing.
  3. Glavach,Mark A.; Campbell, Jr.,John T.; Miller,Scott A.; Overstreet,Keith A.; Sadowski,Randall P.; Sturrock,David T., Automatic tracking of a lot of items through virtual sublots.
  4. Wu, Kan; Lo, Chiang-Chou; Lai, Po-Chun; Chen, Hsu-Jen; Chien, Ming-Cheng; Hung, Wei-Jai, Balancing work release based on both demand and supply variables.
  5. Wegerich, Stephan W., Complex signal decomposition and modeling.
  6. Wegerich, Stephan W.; Wolosewicz, Andre; Pipke, R. Matthew, Diagnostic systems and methods for predictive condition monitoring.
  7. Chen,Yen Hung, Dispatch method and system.
  8. Aqlan, Faisal; Becker, Kevin F.; McAllister, Jason; Tiano, Anthony G., Dynamic batch size and internal transportation.
  9. Shimizu, Michiyuki, Fabrication method of semiconductor integrated circuit device.
  10. Herzog, James P., Kernel-based method for detecting boiler tube leaks.
  11. Cho, Dae-Sik; Chae, Hee-Sun; Kim, Seok-Hyun; Tong, Seung-Hoon; Yoon, Tae-Yang; Kwak, Doh-Soon; Kang, Hee-Se; Park, Yll-Seug; Oh, Jae-Seok, Lots dispatching method for variably arranging processing equipment and/or processing conditions in a succeeding process according to the results of a preceding process and apparatus for the same.
  12. Barker Brian C. ; Bauer Lawrence R. ; Chaloux Susan E. ; Federico John T. ; Hartswick Perry G., Method and apparatus for controlling product routing in a manufacturing line.
  13. Lin,Kuo Chen; Hsieh,Ming Hong, Method and apparatus for displaying production data for improved manufacturing decision making.
  14. Tsuneo Yasuda JP, Method and apparatus for processing order control.
  15. Hilario Oh, Method and apparatus for resolving conflicts in a substrate processing system.
  16. Oh, Hilario, Method and apparatus for resolving conflicts in a substrate processing system.
  17. Oh, Hilario, Method and apparatus for resolving conflicts in a substrate processing system.
  18. Lin, Chien-Yu; Liu, Li-Wen; Chen, Ni-Chung; Wen, Liao-Hon, Method and computer program for using tool performance data for dynamic dispatch of wafer processing to increase quantity of output.
  19. Houle, Dale T., Method and system for determining the relative priority of in-process work and focusing process improvements.
  20. Patel, Nital S.; Jenkins, Steven T., Method and system for dispatching semiconductor lots to manufacturing equipment for fabrication.
  21. Lin, Cheng; Jumahri, Nurulhuda Binte, Method and system for wafer lot order.
  22. Yang Tai-Yi,TWX ; Huang Yu-Feng,TWX ; Chen Wen-Yao,TWX, Method for allocating bottleneck resources.
  23. Lin Li-Ren,TWX, Method for controlling lots dispatches of tool groups.
  24. Huang, Liang-Kai; Lu, Span; You, Ren-Chyi; Hsu, Kuang-Huan, Method for controlling queue time constraints in a fabrication facility.
  25. Ming-Hsiu Hsieh TW; Fu-Kang Lai TW; Wen-Feng Wu TW; Yi-Hsin Chan TW; Yao-Tung Liu TW; Yi-Chin Hsu TW, Method for minimizing total test time for testing factories.
  26. Burda, Richard Gerard; Degbotse, Alfred; Denton, Brian Trevor; Fordyce, Kenneth Jeffrey; Milne, Robert John, Method of release and product flow management for a manufacturing facility.
  27. Volant,Richard P.; Jones,Bradley P.; Shikalgar,Sameer T.; Toner,Michael J.; Wu,Yutong, Methods, systems, and computer program products for managing movement of work-in-process materials in an automated manufacturing environment.
  28. Volant,Richard P.; Jones,Bradley P.; Shikalgar,Sameer T.; Toner,Michael J.; Wu,Yutong, Methods, systems, and computer program products for managing movement of work-in-process materials in an automated manufacturing environment.
  29. Govind, Nirmal; Iyer, Bala; Lockwood, Charles S.; Wuerfel, James R.; Lopez, Peter J., Optimization-based process scheduling method and system.
  30. Oh, Hilario, Recipe cascading in a wafer processing system.
  31. Oh,Hilario, Recipe cascading in a wafer processing system.
  32. Wegerich, Stephan W.; Pipke, Robert Matthew, Residual signal alert generation for condition monitoring using approximated SPRT distribution.
  33. Babikian, Dikran; Oh, Hilario, Robot pre-positioning in a wafer processing system.
  34. Hines, J. Wesley, Robust distance measures for on-line monitoring.
  35. Heskin, James; Shepheard, Mark; Lafoy, Julia, Scheduling system and method.
  36. Heskin,James; Shepheard,Mark; Lafoy,Julia, Scheduling system and method.
  37. Wu, Sunny; Tsen, Yen-Di; Lin, Chun-Hsien; Hui, Keung; Wang, Jo Fei; Mou, Jong-I, Semiconductor processing dispatch control.
  38. Wu, Sunny; Tsen, Yen-Di; Lin, Chun-Hsien; Hui, Keung; Wang, Jo Fei; Mou, Jong-I, Semiconductor processing dispatch control.
  39. Wu, Sunny; Tsen, Yen-Di; Lin, Chun-Hsien; Hui, Keung; Wang, Jo Fei; Mou, Jong-I, Semiconductor processing dispatch control.
  40. Englhardt, Eric Andrew; Shah, Vinay, Small lot size lithography bays.
  41. Tateyama, Masanori; Fujimaru, Syuzo, Substrate processing system and substrate processing method.
  42. Chang, Yao Hsiung; Ho, Chien Peng; Chen, Jau Huang, System and method for automated dispatch and transportation of work-in-process.
  43. Lee,Hsing Hung; Sun,King Chuan; Shen,You Wei; Lee,Yao Chin, System and method for integrating a dispatching system with multiple process lines in a semiconductor manufacturing environment.
  44. Chien, Wen-Chi; Lin, Yu-Wen, System and method for lot priority adjustment.
  45. Goh, Jimmy Lay Kuan; Quek, Meng Yong; Kong, Siow Ling, System for determining potential lot consolidation during manufacturing.
  46. Rice, Michael R.; Englhardt, Eric A.; Shah, Vinay; Elliott, Martin R.; Lowrance, Robert B.; Hudgens, Jeffrey C., Systems and methods for transferring small lot size substrate carriers between processing tools.
  47. Wu Hsueh-Cheng,TWX ; Lin Li-Ren,TWX ; Tsay Yuh-Dean,TWX, Visualizing methods for dispatch and diagnosis of finite machines for semiconductor's manufacturing.

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