초록 ▼

A process has been developed that allows reliable fabrication of vias, used for multi-level wiring purposes. The process features the use of a metallization structure, overlying a pillar structure in a specific area, resulting in a raised and extended metal surface, in areas of overlap. The raised a

A process has been developed that allows reliable fabrication of vias, used for multi-level wiring purposes. The process features the use of a metallization structure, overlying a pillar structure in a specific area, resulting in a raised and extended metal surface, in areas of overlap. The raised and extended metal surface is used for subsequent via contact. Spin on glass processes are also employed to fill narrow spaces between metal structures.

대표청구항 ▼

[ What is claimed is:] [1.] A method for fabricating a MOSFET device, on a semiconductor substrate, using an optimized via hole fabrication process, comprising the steps of:providing an element of said MOSFET device, in a first region of said semiconductor substrate;depositing an insulator layer on

[ What is claimed is:] [1.] A method for fabricating a MOSFET device, on a semiconductor substrate, using an optimized via hole fabrication process, comprising the steps of:providing an element of said MOSFET device, in a first region of said semiconductor substrate;depositing an insulator layer on said semiconductor substrate, including on said element of said MOSFET device;deposition of a pillar metallization layer;patterning of said pillar metallization layer to create metal pillar structure on said insulator layer, in a second region of said semiconductor substrate, with said metal pillar structure having a top surface, with a first width;opening a contact hole in said insulator layer, in a first region of said semiconductor substrate, to said element of said MOSFET device;deposition of a first metallization layer on said metal pillar structure, resulting in raised and extended, top surface of said first metallization layer, in areas in which said first metallization layer resides on underlying said metal pillar structure, with top surface of said first metallization layer having a second width, and deposition of said first metallization layer on exposed top surface of said element, of said MOSFET device, in said contact hole, and deposition of said first metallization layer on said insulator layer, not covered by said metal pillar structure;patterning of said first metallization layer to create a first level metallization structure, comprised of a second portion of said first level metallization structure, overlying said metal pillar structure, in said second region of said semiconductor substrate, and comprised of a first portion of said first level metallization structure, contacting said element, of said MOSFET device, in said contact hole, in said first region of said semiconductor substrate, and resulting in said second portion of said first level metallization structure, in said second region of said semiconductor substrate, having a top surface, comprised of said second width, wider then the top surface of said underlying metal pillar structure, comprised with said first width;deposition of a first dielectric layer on said first level metallization structure, and on said insulator layer, not covered by said first level metallization structure;application of a spin on glass layer on said first dielectric layer, filling the spaces between first level metallization structures, and completely covering said first level metallization;baking of said spin on glass layer;curing of said spin on glass layer;dry etching to remove said spin on glass material from said raised and extended top surface, on said second portion of said first level metallization structure, still leaving said spin on glass material on non-raised area of said first level metallization structure, and in spaces between said first level metallization structures;deposition of a second dielectric layer on said raised and extended top surface, on said second portion of said first level metallization structure, and on said spin on glass, in spaces between said first level metallization structures;opening a via hole in said second dielectric layer, to expose an area of said raised and extended, top surface, in said second portion of said first level metallization structure;deposition of a second metallization layer on said raised and extended top surface, of said second portion of said first level metallization structure, in said via hole, and on said second dielectric layer; andpatterning of said second metallization layer to form second level metallization structure, contacting said raised and extended top surface, of said second portion of said first level metallization structure, in said via hole.