초록

A watchdog timer circuit includes a cyclic counter having an overflow signal that functions as a reset pulse to a microprocessor. The timer circuit includes a feature for selectively supplanting the overflow signal to enable in situ programming of the microprocessor.

대표청구항 ▼

[ I claim:] [1.] An improved watchdog timer circuit for monitoring a microprocessor and resetting the microprocesser upon detection of aberrant operation that allows in situ programming of the microprocessor, the circuit comprising:a timer for generating timing pulses of specified frequency;a cyclic

[ I claim:] [1.] An improved watchdog timer circuit for monitoring a microprocessor and resetting the microprocesser upon detection of aberrant operation that allows in situ programming of the microprocessor, the circuit comprising:a timer for generating timing pulses of specified frequency;a cyclic counter with an overflow bit which functions as a reset pulse to the microprocessor, the counter being of the type for incrementing or decrementing a stored count in accordance with the pulses of said timer; anda switching means for selectively supplanting the overflow signal of said counter with an external programming reset signal to enable in situ programming of the microprocessor.