초록 ▼

A microcomputer integrated circuit (102) has a central processing unit (CPU) (702) first power management circuit (708) responsive to a system management interrupt (SMI) input for controlling operations of the CPU (702). A card interface integrated circuit (112) is adapted for coupling a card (24) t

A microcomputer integrated circuit (102) has a central processing unit (CPU) (702) first power management circuit (708) responsive to a system management interrupt (SMI) input for controlling operations of the CPU (702). A card interface integrated circuit (112) is adapted for coupling a card (24) to the microcomputer integrated circuit (102) and has a second power management circuit logic (1620, 1630) that responds to a plurality of interrupt event inputs (in CSC REGs A, B) and concentrates these inputs to a single card system management interrupt output (CRDSMI#). A peripheral processor integrated circuit (110) has a third power management circuit (920) including a plurality of system management interrupt (SMI) sources, and a SMI unit (2370). The SMI unit (2370) has an output (SMI#) connected to the SMI input of the microprocessor integrated circuit. The SMI unit (2370) responds to the card SMI output of the card interface integrated circuit (112) as well as the plurality of SMI sources. The plurality of SMI sources includes timer circuitry (2350) connected to power down terminals (IDEPWR#, FDDPWR#, SIUPWR#, PCSPWR#) for connection to external peripherals upon respective timeouts in the timer circuitry (2350). Other circuits, systems and methods are also described.

대표청구항 ▼

[ What is claimed is:] [1.] A computer system comprising:a first integrated circuit having a central processing unit (CPU) and a first power management circuit having a system management interrupt (SMI) input;a second integrated circuit having a second power management circuit responsive to one or m

[ What is claimed is:] [1.] A computer system comprising:a first integrated circuit having a central processing unit (CPU) and a first power management circuit having a system management interrupt (SMI) input;a second integrated circuit having a second power management circuit responsive to one or more interrupt event inputs and concentrating these inputs to a single second integrated circuit system management interrupt (SMI) output; anda third integrated circuit having a third power management circuit including one or more system management interrupt (SMI) sources, said third power management circuit having an output connected to said SMI input of said first integrated circuit, and said third power management circuit responsive to said second integrated circuit SMI output as well as said one or more SMI sources.