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Memory system having non-volatile data storage structure for memory control parameters and method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-008/00
출원번호 US-0850582 (1997-05-02)
발명자 / 주소
  • Roohparvar Frankie F.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner & Kluth, P.A.
인용정보 피인용 횟수 : 58  인용 특허 : 12

초록

A memory system capable of being configured for optimum operation after fabrication and method of controlling same. The system includes an array of memory cells arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word

대표청구항

[ I claim:] [1.] A memory system comprising:an array of memory cells arranged in a multiplicity of rows and a multiplicity of columns, with each cell being located in one of the rows and each cell being located in one of the columns;a control for controlling memory operations, with the operations in

이 특허에 인용된 특허 (12)

  1. Roohparvar Frankie F. (Cupertino CA), Apparatus for entering and executing test mode operations for memory.
  2. Roohparvar Frankie (Cupertino CA), Circuit and method for performing tests on memory array cells using external sense amplifier reference current.
  3. Atsumi Shigeru (Tokyo JPX) Banba Hironori (Kawasaki JPX), Data latch circuit having non-volatile memory cell.
  4. Gee Lubin (Santa Clara CA) Cheng Pearl (Sunnyvale CA) Bobra Yogendra (Santa Clara CA) Mehta Rustam (Sunnyvale CA), Intelligent electrically programmable and electrically erasable ROM.
  5. Roohparvar Frankie F. (Cupertino CA), Memory system having non-volatile data storage structure for memory control parameters and method.
  6. Roohparvar Frankie F. (Cupertino CA) Chevallier Christophe J. (Palo Alto CA), Memory system having programmable flow control register.
  7. Roohparvar Frankie F. (Cupertino CA), Memory system with non-volatile data storage unit and method of initializing same.
  8. Roohparvar Frankie F. (Cupertino CA), Memory system with non-volatile data storage unit and method of initializing same.
  9. Bohac ; Jr. Frank J. (Laguna Hills CA), Nonvolatile latch.
  10. Castro Hernan A. (Shingle Springs CA), Reset circuit for redundant memory using CAM cells.
  11. Clavelle Stella L. (3824 Deercreek La. Harvey LA 70058), Skin heat shield system.
  12. Kowshik Vikram (San Jose CA) Lucero Elroy M. (San Jose CA), Zero power, electrically alterable, nonvolatile latch.

이 특허를 인용한 특허 (58)

  1. Dean Gans ; Eric J. Stave ; Joseph Thomas Pawlowski, Adjustable I/O timing from externally applied voltage.
  2. Sutardja, Pantas; Wu, Albert; Chang, Runzi; Lee, Winston; Lee, Peter, Apparatus and method for repairing resistive memories and increasing overall read sensitivity of sense amplifiers.
  3. Frankie F. Roohparvar, Apparatus for externally timing high voltage cycles of non-volatile memory system.
  4. Roohparvar Frankie F., Apparatus for externally timing high voltage cycles of non-volatile memory system.
  5. Roohparvar, Frankie F., Apparatus for externally timing high voltage cycles of non-volatile memory system.
  6. Roohparvar, Frankie F., Apparatus for externally timing high voltage cycles of non-volatile memory system.
  7. Sheldon Peter ; Schnizlein Paul ; Hendrickson Alan, Battery monitor with software trim.
  8. Sau Ching Wong ; Kimberley Johnsen, Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell.
  9. Cornwell, Michael J.; Dudte, Christopher P., Disabling faulty flash memory dies.
  10. Cornwell, Michael J.; Dudte, Christopher P., Disabling faulty flash memory dies.
  11. Wong, Sau Ching, Dynamic refresh that changes the physical storage locations of data in flash memory.
  12. Ngo, Quan H.; Monasa, Saad, Enabling an interim density for top boot flash memories.
  13. Naso,Giovanni; Santin,Giovanni, Flash cell fuse circuit.
  14. Santin, Giovanni; Naso, Giovanni, Flash cell fuse circuit.
  15. Santin, Giovanni; Naso, Giovanni, Flash cell fuse circuit.
  16. Santin,Giovanni; Naso,Giovanni, Flash cell fuse circuit.
  17. Sau Ching Wong, Flash memory with dynamic refresh.
  18. Cornwell, Michael J.; Dudte, Christopher P.; Wakrat, Nir Jacob, Initiating memory wear leveling.
  19. Tsao, Cheng-Chung; Lin, Tien-ler, Integrated circuit memory device having interleaved read and program capabilities and methods of operating same.
  20. Cornwell, Michael J.; Dudte, Christopher P., Interleaving policies for flash memory.
  21. Hollmer Shane C. ; Le Binh Quang ; Chen Pau-Ling, Memory system having a program and erase voltage modifier.
  22. Cornwell, Michael J.; Dudte, Christopher P., Monitoring health of non-volatile memory.
  23. Sau-Ching Wong, Multi-bit-cell non-volatile memory with maximized data capacity.
  24. Wong, Sau-Ching, Multi-bit-per-cell memory system with numbers of bits per cell set by testing of memory units.
  25. Mu, Fuchen; He, Chen; Wang, Yanzhuo, Non-volatile memory (NVM) with dynamically adjusted reference current.
  26. Roohparvar, Frankie F., Non-volatile memory device with erase address register.
  27. Roohparvar, Frankie F., Non-volatile memory device with erase address register.
  28. Roohparvar, Frankie F., Non-volatile memory device with erase address register.
  29. Roohparvar, Frankie F., Non-volatile memory device with erase address register.
  30. Roohparvar, Frankie F., Non-volatile memory device with erase address register.
  31. Roohparvar, Frankie F., Non-volatile memory device with erase address register.
  32. Roohparvar,Frankie F., Non-volatile memory device with erase address register.
  33. Roohparvar,Frankie F., Non-volatile memory device with erase address register.
  34. Frankie F. Roohparvar, Non-volatile memory device with erase cycle register.
  35. Frankie F. Roohparvar, Non-volatile memory device with erase register.
  36. Roohparvar, Frankie Fariborz, Non-volatile memory having a control mini-array.
  37. Roohparvar, Frankie Fariborz, Non-volatile memory having a control mini-array.
  38. Wong, Sau Ching, Non-volatile memory operations that change a mapping between physical and logical addresses when restoring data.
  39. Pawletko Joseph G. ; Han K. Michael ; Derhacobian Narbeh, Nonlinear stepped programming voltage.
  40. Akamatsu, Toshihiro, Nonvolatile semiconductor storage device and control method thereof.
  41. Bettman Roger, Optimized programming/erase parameters for programmable devices.
  42. Wong,Sau Ching, Periodic refresh operations for non-volatile multiple-bit-per-cell memory.
  43. Wong, Sau Ching, Refresh operations that change address mappings in a non-volatile memory.
  44. Pawletko Joseph G. ; Le Binh Quang ; Chen Pau-Ling ; Hong James M., Register driven means to control programming voltages.
  45. Cornwell, Michael J.; Dudte, Christopher P.; Fisher, Jr., Joseph R., Reporting flash memory operating voltages.
  46. Cornwell, Michael J.; Dudte, Christopher P.; Fisher, Jr., Joseph R., Reporting flash memory operating voltages.
  47. Fagan, John L.; Bossard, Mark, Selectable delay pulse generator.
  48. Masahiro Hosoda JP, Semiconductor memory device that is tested even with fewer test pins.
  49. Kim, Jung Pill; Kim, Taehyun; Kim, Sungryul; Kim, Daeik D., Sense amplifier offset voltage reduction.
  50. Alrod, Idan; Sharon, Eran, Storage device and method including accessing a word line of a memory using parameters selected according to groups of word lines.
  51. Alrod, Idan; Sharon, Eran, Storage device and method using parameters based on physical memory block location.
  52. Han K. Michael ; Pawletko Joseph G. ; Derhacobian Narbeh ; Chang Chi, Symmetrical program and erase scheme to improve erase time degradation in NAND devices.
  53. Tamassia, Hugh Robert; Stransky, Peter Franklin; Acharya, Ravi; Ranganath, Satyan, System and methods for mobile ordering and payment.
  54. Pawletko Joseph G. ; Le Binh Quang ; Hong James M. ; Chen Pau-Ling, System for erasing a memory cell.
  55. Pawletko Joseph G. ; Le Binh Quang ; Chen Pau-Ling ; Hong James M., System for programming memory cells.
  56. Tamassia, Hugh Robert; Stransky, Peter Franklin; Acharya, Ravi; Avatara, Satyan, Systems and methods for mobile ordering and payment.
  57. Tamassia, Hugh Robert; Stransky, Peter Franklin; Acharya, Ravi; Ranganath, Satyan, Systems and methods for mobile ordering and payment.
  58. Cornwell, Michael J.; Dudte, Christopher P.; Wakrat, Nir Jacob, Updating error correction codes for data blocks.
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