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An apparatus and method are shown for decoding variable length instructions in a processor where a line of variable length instructions from an instruction cache are loaded into an instruction buffer and the start bits indicating the instruction boundaries of the instructions in the line of variable

An apparatus and method are shown for decoding variable length instructions in a processor where a line of variable length instructions from an instruction cache are loaded into an instruction buffer and the start bits indicating the instruction boundaries of the instructions in the line of variable length instructions is loaded into a start bit buffer. A first shift register is loaded with the start bits and shifted in response to a lower program count value which is also used to shift the instruction buffer. A length of a current instruction is obtained by detecting the position of the next instruction boundary in the start bits in the first register. The length of the current instruction is added to the current value of the lower program count value in order to obtain a next sequential value for the lower program count which is loaded into a lower program count register. An upper program count value is determined by loading a second shift register with the start bits, shifting the start bits in response to the lower program count value and detecting when only one instruction remains in the instruction buffer. When one instruction remains, the upper program count value is incremented and loaded into an upper program count register for output to the instruction cache in order to cause a fetch of another line of instructions and a `0` value is loaded into the lower program count register. Another embodiment of the present invention includes multiplexors for loading a branch address into the upper and lower program count registers in response to a branch control signal.

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[ We claim:] [1.] An instruction decoding circuit for decoding variable length instructions having instruction boundary markers, the instruction decoding circuit comprising:an instruction sequencing circuit configured to generate an instruction cache line address signal which selects a line of varia

[ We claim:] [1.] An instruction decoding circuit for decoding variable length instructions having instruction boundary markers, the instruction decoding circuit comprising:an instruction sequencing circuit configured to generate an instruction cache line address signal which selects a line of variable length instructions from an instruction cache and which is further configured to detect an end of instruction cache line condition and, responsive thereto, select another line of variable length instructions, and still further wherein the instruction sequencing circuit is configured to receive the instruction boundary markers corresponding to the line of variable length instructions, detect a boundary of each variable length instruction in the line of variable length instructions and, responsive thereto, generate an instruction buffer control signal;an instruction buffer configured to receive and store the line of variable length instructions from the instruction cache, wherein the instruction buffer is further configured to receive the instruction buffer control signal and, responsive thereto, shift the line of variable length instructions to a most significant position of the instruction buffer responsive to the instruction boundary markers such that each variable length instruction in the line of variable length instructions is selected for output from the instruction buffer by the instruction buffer control signal.