$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Removal of extended bond pads using intermetallics 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-029/54
  • H01L-023/485
출원번호 US-0717411 (1996-09-20)
발명자 / 주소
  • Galloway Terry R.
출원인 / 주소
  • Integrated Device Technology, Inc.
대리인 / 주소
    Majestic, Parsons, Siebert & Hsue
인용정보 피인용 횟수 : 24  인용 특허 : 20

초록

Removable extension areas electrically connected to the original die bond pad allow for testing connections to be made. After removal of the extension areas, the circuitry below the region of the extension areas can be seen through a microscope. The use of perforations and/or underlayer sections can

대표청구항

[ What is claimed is:] [1.] A structure comprising:a die;a wire bond pad on the die;an extension area electrically connected to the wire bond pad, the extension area comprising a first type of metal, the extension area extending, beyond the area of the wire bond pad;a barrier layer separating the wi

이 특허에 인용된 특허 (20)

  1. Bergeron Richard J. (Essex Junction VT) LaMothe Thomas J. (Georgia VT) Suarez Joseph E. (Burlington VT) Thompson John A. (Monkton Ridge VT), Additive structure and method for testing semiconductor wire bond dies.
  2. Baker Thomas R. (Tempe AZ) Anderson George F. (Tempe AZ), Bonding pad for semiconductor devices.
  3. Nolan Ernest R. (Round Rock TX) Duane Diana C. (Cedar Park TX) Herder Todd H. (Corvallis OR) Bishop Thomas A. (Austin TX) Tran Kimcuc T. (Austin TX) Froehlich Robert W. (Austin TX) German Randy L. (A, Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same.
  4. Golshan Shahin (Midland TX) St. Martin Craig A. (Midland TX) Rhodine Craig W. (Midland TX), Configuration and method for positioning semiconductor device bond pads using additional process layers.
  5. Albergo Christopher J. (Penfield NY) Reele Samuel (Rochester NY), Electrode structure for light emitting diode array chip.
  6. Sako Shigeki (Yokohama JPX), Hybrid resin-sealed semiconductor device.
  7. Cusack Michael D. (Monument CO) Hagen Michael P. (Colorado Springs CO) Larkin James E. (Colorado Springs CO), Integrated circuit having an improved bond pad.
  8. Kierse Oliver J. (Clare County IEX), Integrated circuit package with improved heat dissipation.
  9. Farnworth Warren (Nampa ID) Wood Alan (Boise ID), Method and apparatus for manufacturing known good semiconductor die.
  10. Akram Salman (Boise ID) Farnworth Warren M. (Nampa ID) Wood Alan G. (Boise ID), Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice.
  11. Baker Mark H. (San Jose CA), Method for forming solder bumps in semiconductor devices.
  12. Hatada Kenzo (Katano JPX), Method of bonding semiconductor devices together.
  13. Kumar Nalin (Austin TX) Goruganthu Rama R. (Austin TX) Ghazi Mohammed K. (Austin TX), Method of making semiconductor bonding bumps using metal cluster ion deposition.
  14. Garcia Enrique (Sandy Hook CT), Semiconductor chip with recessed bond pads.
  15. Hosomi Eiichi (Kawasaki JPX) Takubo Chiaki (Yokohama JPX) Tazawa Hiroshi (Ichikawa JPX) Miyamoto Ryouichi (Kawasaki JPX) Arai Takashi (Oita JPX) Shibasaki Koji (Kawasaki JPX), Semiconductor device comprising fine bump electrode having small side etch portion and stable characteristics.
  16. Okumura Tomisaburo (Kyoto JA) Matsuo Takatoshi (Kyoto JA), Semiconductor device having bonding pads extending over active regions.
  17. Mizushima Kazuyuki (Tokyo JPX), Semiconductor device with an electrode pad having increased mechanical strength.
  18. Oku Kazutoshi (Hyogo JPX) Hirosue Masahiro (Hyogo JPX), Semiconductor device with an elevated bonding pad.
  19. Schroeder Jack A. ; Monroe Conrad S., Structure having flip-chip connected substrates.
  20. Lam Ken (Colorado Springs CO), TAB testing of area array interconnected chips.

이 특허를 인용한 특허 (24)

  1. Yamane,Tae, Chip-size semiconductor package.
  2. Daubenspeck,Timothy H.; Gambino,Jeffrey P.; Muzzy,Christopher D.; Sauter,Wolfgang, Contour structures to highlight inspection regions.
  3. Paul Davis Bell, Integrated circuit having wirebond pads suitable for probing.
  4. Danziger, Steve M.; Shah, Tushar, Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects.
  5. Danziger, Steve M; Shah, Tushar, Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects.
  6. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang, Method of creating contour structures to highlight inspection region.
  7. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  8. Kasai Kunihiro,JPX, Method of manufacturing semiconductor device having a test pad.
  9. Siniaguine, Oleg; Savastiouk, Sergey, Packaging of integrated circuits and vertical integration.
  10. Nakamura,Hirotake, Recording head unit, method of manufacturing the same, and recording apparatus using the unit.
  11. Kanai,Tomonori; Kishimoto,Kiyoharu; Kikuchi,Yuji, Semiconductor device.
  12. Paul Davis Bell, Structure and method for probing wiring bond pads.
  13. Leistiko, Tyson; Kao, Huahung, Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types.
  14. Leistiko, Tyson; Kao, Huahung, Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types.
  15. Leistiko, Tyson; Kao, Huahung; Loeb, Wayne A., Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types.
  16. Loeb, Wayne; Leistiko, Tyson; Kao, Huahung, Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types.
  17. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  18. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  19. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  20. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  21. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin,Mou Shiung; Chen,Michael; Chou,Chien Kang; Chou,Mark, Wirebond pad for semiconductor chip or wafer.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로