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A parallel processing system composed of a regular array of programmable logic devices, each of which can be configured to perform any logical mapping from inputs to outputs. The configuration of each device is specified by a small program memory contained inside each device. Any device's program me

A parallel processing system composed of a regular array of programmable logic devices, each of which can be configured to perform any logical mapping from inputs to outputs. The configuration of each device is specified by a small program memory contained inside each device. Any device's program memory can be read or written by any other device connected to it within the array. This facilitates the development of extremely parallel systems whose configuration can be modified at runtime, while distributing control of the array throughout the entire array itself. The resulting system is thus completely self-reconfigurable, avoiding the bottlenecks and critical failure points found in inherently externally-configured systems.

대표청구항 ▼

[ What is claimed is:] [1.] A programmable logic device comprising:(a) a first plurality of input channels,(b) a means of computing the value of a binary state variable from said first plurality of input channels,(c) an internal storage memory accessible as either a serial read serial write shift re

[ What is claimed is:] [1.] A programmable logic device comprising:(a) a first plurality of input channels,(b) a means of computing the value of a binary state variable from said first plurality of input channels,(c) an internal storage memory accessible as either a serial read serial write shift register or as a parallel read random access memory, depending on the value of said binary state variable,(d) a second plurality of input channels which correspond one to one with said first plurality of input channels,(e) a means of combining said first plurality of input channels and said second plurality of input channels to specify serial input data for said shift register,(f) a means of addressing said random access memory using said second plurality of input channels,(g) a plurality of output channels, each of which correspond to either one of said first plurality of input channels or one of said second plurality of input channels,(h) a means of setting the values of said plurality of output channels by combining said first plurality of input channels with either the serial output or parallel outputs of said internal storage memory, depending on the value of said binary state variable, and(i) a means of shifting said shift register's contents based on the value of said binary state variable and an externally applied dock, reby said programmable logic device can map inputs to output via said internal storage memory, or can present the contents of said memory to certain of its outputs and can load the contents of said memory from certain of its inputs.