초록 ▼

Disclosed is a NOR type mask ROM device with a hierarchical bit line architecture in which metal oxide semiconductor FETs constituting memory cells are connected in parallel to one another. The mask ROM device is implemented with an address transition detection (ATD) circuit, and comprises first and

Disclosed is a NOR type mask ROM device with a hierarchical bit line architecture in which metal oxide semiconductor FETs constituting memory cells are connected in parallel to one another. The mask ROM device is implemented with an address transition detection (ATD) circuit, and comprises first and second bit lines arranged in the ratio of 2:1, ground lines corresponding to the second bit lines, respectively, first switches each connected between an end of a corresponding odd-numbered bit line of the first bit lines and an end of a corresponding bit line of the second bit lines, second switches each connected between an end of a corresponding even-numbered bit line of the second bit lines and an end of a corresponding ground line of the ground lines, and a charging circuit for charging at least one adjacent non-selected bit line of the first bit lines at both sides of at least one selected bit line of the first bit lines to a predetermined voltage level, when a precharging operation is carried out to sense data through at least one selected bit line of the second bit lines.

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor read only memory having an hierarchical bit line architecture, comprising:a plurality of first bit lines;a plurality of memory cell groups each connected between two adjacent bit lines of the first bit lines;a plurality of second bit lines, the first and s

[ What is claimed is:] [1.] A semiconductor read only memory having an hierarchical bit line architecture, comprising:a plurality of first bit lines;a plurality of memory cell groups each connected between two adjacent bit lines of the first bit lines;a plurality of second bit lines, the first and second bit lines being in the ratio of 2:1;a plurality of ground lines corresponding to the second bit lines, respectively;a plurality of first switches each connected between an end of a corresponding odd-numbered bit line of the first bit lines and an end of a corresponding bit line of the second bit lines;a plurality of second switches each connected between an end of a corresponding even-numbered bit line of the second bit lines and an end of a corresponding ground line of the ground lines; andmeans for charging at least one adjacent non-selected bit line of the first bit lines at both sides of at least one selected bit line of the first bit lines to a predetermined voltage level, when a precharging operation is carried out to sense data through at least one selected bit line of the second bit lines.