초록 ▼

A technique for providing a compare-and-exchange (CMPXCHG) instruction which may be implemented in an instruction set requiring a limited number of source and destination operands for each instruction in the instruction set. In order to utilize an instruction to perform a read-modify-write operation

A technique for providing a compare-and-exchange (CMPXCHG) instruction which may be implemented in an instruction set requiring a limited number of source and destination operands for each instruction in the instruction set. In order to utilize an instruction to perform a read-modify-write operation three source and one destination operands are needed to supply the location of various information used in executing the instruction. Instead of providing all four operands with the instruction, the CMPXCHG instruction of the present invention utilizes an implied operation-specific register. This register is implied in the instruction when the CMPXCHG instruction is executed, so that only two source operands are needed with the CMPXCHG instruction.

대표청구항 ▼

[ We claim:] [1.] A computer system for executing an instruction that performs a read-modify-write operation comprising:a plurality of processors, at least a first processor having an execution unit that executes said instruction and a register file that stores first and second source operands assoc

[ We claim:] [1.] A computer system for executing an instruction that performs a read-modify-write operation comprising:a plurality of processors, at least a first processor having an execution unit that executes said instruction and a register file that stores first and second source operands associated with said instruction;a memory having a memory space shared by said plurality of processors;a register coupled to said execution unit that functions as a source of a reference value during a first operation of said instruction, and as a destination that stores a lock value identified by said first source operand during a subsequent operation of said instruction;a lock storage location coupled to said execution unit that stores data which controls access to said memory space;wherein said first operation compares said lock value with said reference value, a true comparison resulting in said lock value being stored in said register during said subsequent operation, with data identified by said second source operand being written to said lock storage location, an untrue comparison resulting in said lock value being stored in said register during said subsequent operation, with data identified by said first source operand being written to said lock storage location.