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Semiconductor package integral with semiconductor chip 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03L-023/528
출원번호 US-0537396 (1995-10-02)
우선권정보 JP-0221827 (1995-08-30)
발명자 / 주소
  • Iwasaki Hiroshi,JPX
  • Aoki Hideo,JPX
출원인 / 주소
  • Kabushiki Kaisha Toshiba, JPX
대리인 / 주소
    Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
인용정보 피인용 횟수 : 97  인용 특허 : 7

초록 ▼

A semiconductor chip having a semiconductor substrate, a plurality of pads formed above the semiconductor substrate a first passivating film formed over an entire surface of the semiconductor substrate, and having openings above the pads the surface of the first passivating film being flat, a plural

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor package comprising:a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substrate, and a first passivating film formed over an entire surface of said semiconductor substrate and having openings above sa

이 특허에 인용된 특허 (7)

  1. Cook Herbert C. (Jericho VT) Farrar ; Sr. Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Motsiff William T. (Essex Junction VT) Wirsing Adolf E. (South Hero VT), Metallization composite having nickle intermediate/interface.
    상세보기
  2. Kondo Kenji (Hoi JPX) Kunda Hachiro (Chiryu JPX) Sonobe Toshio (Okazaki JPX), Method for making a semiconductor device.
    상세보기
  3. Schilling ; Hartmut, Multilayer interconnected structure for semiconductor integrated circuit.
    상세보기
  4. Hirano Naohiko (Yokohama JPX), Multilayer package.
    상세보기
  5. Chao Chien-Chi (Taipei TWX) Lin Ming-Hane (Chu-Pei TWX) Ho Ted C. (Hsinchu TWX), Packaging assembly with consolidated common voltage connections for integrated circuits.
    상세보기
  6. Uda Takayuki (Ohme JPX) Hiramoto Toshiro (Ohme JPX) Tamba Nobuo (Ohme JPX) Ishida Hisashi (Higashiyamato JPX) Akimoto Kazuhiro (Akishima JPX) Odaka Masanori (Kodaira JPX) Tanaka Tasuku (Hamura JPX) H, Semiconductor integrated circuit device and methods for production thereof.
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  7. Owada Nobuo (Ohme JPX) Oogaya Kaoru (Ohme JPX) Kobayashi Tohru (Iruma JPX) Kawaji Mikinori (Hino JPX), Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wir.
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이 특허를 인용한 특허 (97)

  1. Takahiro Iijima JP; Akio Rokugawa JP, Build-up board package for semiconductor devices.
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  2. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
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  3. Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Li-Ren; Lo, Hsin-Jung, Chip package and method for fabricating the same.
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  4. Lin, Mou-Shiung; Lin, I, Shih-Hsiung, Chip package having a chip combined with a substrate via a copper pillar.
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  5. Chen, Ke-Hung; Lin, Shih-Hsiung; Lin, Mou-Shiung, Chip package with dam bar restricting flow of underfill.
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  6. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
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  7. Peter R. Ewer GB, Chip scale package.
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  8. Ewer Peter R.,GBX, Chip scale packaging process.
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  9. Shinogi Hiroyuki,JPX ; Takai Nobuyuki,JPX ; Tokushige Ryoji,JPX ; Takao Yukihiro,JPX ; Kitagawa Katsuhiko,JPX, Chip size package and manufacturing method thereof.
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  10. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
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  11. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
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  12. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
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  13. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
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  14. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
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  15. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Cylindrical bonding structure and method of manufacture.
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  16. Nobuaki Hashimoto JP, Film carrier tape.
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  18. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
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  19. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
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  20. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
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  21. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
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  22. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  23. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  24. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  25. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  26. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  27. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  28. Chakravorty Kishore K., Low cost chip size package and method of fabricating the same.
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  29. Kishore K. Chakravorty, Low cost chip size package and method of fabricating the same.
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  30. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
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  31. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
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  32. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
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  33. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
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  34. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
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  35. Lin, Mou-Shiung, Metallization structure over passivation layer for IC chip.
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  36. Masaaki Hayama JP; Noboru Mouri JP; Hayami Matsunaga JP, Method for fabricating a multilayer ceramic substrate.
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  39. Singh Abha R. ; Dixit Girish Anant ; Hsu Wei-Yung ; Xing Guoqiang, Method for reducing recess for the formation of local interconnect and or plug trench fill for etchback process.
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  41. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
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  42. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
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  43. Farnworth,Warren M.; Brooks,Jerry M., Method of wafer bumping for enabling a stitch wire bond in the absence of discrete bump formation.
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  44. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  46. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  48. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  49. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
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  56. Siniaguine, Oleg; Savastiouk, Sergey, Packaging of integrated circuits and vertical integration.
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  80. Lin, Mou-Shiung, Solder interconnect on IC chip.
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  81. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.
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  82. Chou, Chiu-Ming; Lin, Mou-Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
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  94. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  95. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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