$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Multiprocessor system having mapping table in each node to map global physical addresses to local physical addresses of 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/10
출원번호 US-0673043 (1996-07-01)
발명자 / 주소
  • Nesheim William A.
  • Guzovskiy Aleksandr
출원인 / 주소
  • Sun Microsystems, Inc.
대리인 / 주소
    Kubida
인용정보 피인용 횟수 : 79  인용 특허 : 7

초록

In a multiprocessor computing system, virtual memory addresses are mapped to local physical memory addresses of an attraction memory, containing a replication of the data contained at remote physical addresses, in a node of the system. A mapping table is created and maintained in each node of the sy

대표청구항

[ What is claimed is:] [1.] In a computing system having a plurality of nodes, each node having a plurality of CPUs, local memory, a memory management unit, and an address translation unit, the computing system having a page table mapping a virtual address to a physical page address, a method of acc

이 특허에 인용된 특허 (7)

  1. Kelly Edmund (San Jose CA) Cekleov Michel (Mountain View CA) Dubois Michel (Los Angeles CA), Apparatus for maintaining consistency in a multiprocessor computer system using virtual caching.
  2. Sandberg Jonathan (New York NY), Apparatus for providing shared virtual memory among interconnected computer nodes with minimal processor involvement.
  3. Hagersten Erik ; Zak ; Jr. Robert C., Hybrid NUMA COMA caching system and methods for selecting between the caching modes.
  4. Parrish Osey C. (Lauderdale Lakes FL) Peiffer ; Jr. Robert E. (Plantation FL) Thomas James H. (Plantation FL) Hilpert ; Jr. Edwin J. (Greenbelt MD), Memory address mechanism in a distributed memory architecture.
  5. Yamazaki Takeshi (Tokyo JPX), Multiprocessor system for locally managing address translation table.
  6. Costa Maria (Buccinasco ITX) Leonardi Carlo (Legnano ITX), Multiprocessor system having distributed shared resources and dynamic and selective global data replication.
  7. Casamatta Angelo (Cornaredo ITX) Mantellina Calogero (Cerro Maggiore ITX) Zanzottera Daniele (Busto Garolfo ITX), Multiprocessor system with global data replication and two levels of address translation units.

이 특허를 인용한 특허 (79)

  1. O'Krafka, Brian W.; Dinker, Darpan; Krishnan, Manavalan; George, Johann, Approaches for the replication of write sets.
  2. Hagersten Erik E., Cache-less address translation.
  3. Wilkes, John, Centrally managed unified shared virtual address space.
  4. Riddle, Thomas A.; Dinker, Darpan; Eckhardt, Andrew D.; Koster, Michael J., Cluster of processing nodes with distributed global flash memory using commodity server technology.
  5. Lesmanne,Sylvie; Bernard,Christian; Koumou,Pamphile, Coherence controller for a multiprocessor system, module, and multiprocessor system with a multimodule architecture incorporating such a controller.
  6. Michael C. Greim ; James R. Bartlett, DSP intercommunication network.
  7. Greim Michael C. ; Bartlett James R., DSP interrupt control for handling multiple interrupts.
  8. Greim, Michael C.; Bartlett, James R., DSP with distributed RAM structure.
  9. Casamatta Angelo,ITX, Data-processing system with CC-NUMA (cache-coherent, non-uniform memory access) architecture and remote cache incorporated in local memory.
  10. Faanes,Gregory J.; Scott,Steven L.; Lundberg,Eric P.; Moore, Jr.,William T.; Johnson,Timothy J., Decoupled scalar/vector computer architecture system and method.
  11. Scott, Steven L.; Faanes, Gregory J., Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system.
  12. Zhou, Wei; Chu, Chee Hoe; Chang, Po-Chien, Distributed flash memory storage manager systems.
  13. Zhou, Wei; Chu, Chee Hoe; Chang, Po-Chien, Distributed flash memory storage manager systems.
  14. Wong, Kai C., Efficient data transfer between computers in a virtual NUMA system using RDMA.
  15. Busch, John; Dinker, Darpan; Ouye, Darryl, Efficient flash memory-based object store.
  16. Busch, John; Dinker, Darpan; Ouye, Darryl, Efficient flash memory-based object store.
  17. George, Johann; Dinker, Darpan; Krishnan, Manavalan; O'Krafka, Brian W., Efficient recovery of transactional data stores.
  18. Krishnan, Manavalan; Dinker, Darpan; O'Krafka, Brian W., Event processing in a flash memory-based object store.
  19. Kourosh Gharachorloo ; Daniel J. Scales, Extended translation lookaside buffer with fine-grain state bits.
  20. Eckhardt, Andrew D.; Koster, Michael J., Failure recovery using consensus replication in a distributed flash memory system.
  21. Dinker, Darpan, Fine grained adaptive throttling of background processes.
  22. Ouye, Darryl; Dinker, Darpan; Busch, John, Flexible way of specifying storage attributes in a flash memory-based object store.
  23. Colgrove, John; Hayes, John; Miller, Ethan; Sandvig, Cary; Hasbani, Joseph S.; Wang, Feng, Garbage collection in a storage system.
  24. Colgrove, John; Hayes, John; Miller, Ethan; Sandvig, Cary; Hasbani, Joseph S.; Wang, Feng, Garbage collection in a storage system.
  25. Kohn,James R., Indirectly addressed vector load-operate-store method and apparatus.
  26. Chen, Diling; Li, Chuang; Lu, Wei; Xia, Yin Ben; Xiang, Zhe, Installing software onto a client through a network, and corresponding client.
  27. Baker, David Cureton, Integrated circuit with memory-less page table.
  28. Scott, Steven L., Latency tolerant distributed shared memory multiprocessor computer.
  29. Bodwin, James M.; Dinker, Darpan; Eckhardt, Andrew D.; Ouye, Darryl, Low level object version tracking using non-volatile memory write generations.
  30. Bodwin, James M.; Dinker, Darpan; Eckhardt, Andrew D.; Ouye, Darryl M., Low level object version tracking using non-volatile memory write generations.
  31. Sutherland, Danny R.; Tzortzatos, Elpida; Yocom, Peter B., Managing unvirtualized data pages in real storage.
  32. Liu, Yao; Chen, Licheng; Cui, Zehan; Chen, Mingyu, Memory management method and device and memory controller.
  33. Pautsch, Gregory W.; Pautsch, Adam, Method and apparatus for cooling electronic components.
  34. Kohn, James R., Method and apparatus for indirectly addressed vector load-add-store across multi-processors.
  35. Kohn,James R., Method and apparatus for indirectly addressed vector load-add-store across multi-processors.
  36. Betty Y. Kikuta ; James S. Blomgren ; Terence M. Potter, Method and apparatus that enforces a regional memory model in hierarchical memory systems.
  37. Noel,Karen L.; Fisher, Jr.,Wendell B.; Jordan,Gregory H.; Moser,Christian, Method and system of determining attributes of a functional unit in a multiple processor computer system.
  38. Nadia Bouraoui FR; Jean-Pascal Mazzilli FR, Method for controlling memory access on a machine with non-uniform memory access and machine for implementing such a method.
  39. Curtis Priem ; Don Bittel, Method, apparatus and article of manufacture for mapping physical memory in a virtual address system.
  40. Dinker, Darpan, Minimizing write operations to a flash memory-based object store.
  41. Erik E. Hagersten ; Christopher J. Jackson ; Aleksandr Guzovskiy ; William A. Nesheim, Multiprocessing computer system employing a cluster communication error reporting mechanism.
  42. Erik E. Hagersten ; Christopher J. Jackson ; Aleksandr Guzovskiy ; William A. Nesheim, Multiprocessing computer system employing a cluster protection mechanism.
  43. Luick David Arnold ; Willis John Christopher ; Winterfield Philip Braun, Multiprocessor cache coherence directed by combined local and global tables.
  44. Scott,Steven L.; Faanes,Gregory J.; Stephenson,Brick; Moore, Jr.,William T.; Kohn,James R., Multistream processing memory-and barrier-synchronization method and apparatus.
  45. Scott,Steven L.; Dickson,Chris; Reinhardt,Steve, Node translation and protection in a clustered multiprocessor system.
  46. Bruening, Ulrich; Jordan, Richard; Koster, Michael J.; Dinker, Darpan, Non-volatile solid-state storage system supporting high bandwidth and random access.
  47. Michael C. Greim ; James R. Bartlett, Paging method for DSP.
  48. Chinya, Gautham N.; Wang, Hong; Mathaikutty, Deepak A.; Collins, Jamison D.; Schuchman, Ethan; Held, James P.; Bhatt, Ajay V.; Sethi, Prashant; Whalley, Stephen F., Providing hardware support for shared virtual memory between local and remote physical memory.
  49. Chinya, Gautham N.; Wang, Hong; Mathaikutty, Deepak A.; Collins, Jamison D.; Schuchman, Ethan; Held, James P.; Bhatt, Ajay V.; Sethi, Prashant; Whalley, Stephen F., Providing hardware support for shared virtual memory between local and remote physical memory.
  50. George, Johann; O'Krafka, Brian W., Recovery and replication of a flash memory-based object store.
  51. Scott, Steven L.; Faanes, Gregory J.; Stephenson, Brick; Moore, Jr., William T.; Kohn, James R., Relaxed memory consistency model.
  52. Scott, Steven L.; Dickson, Chris; Fromm, Eric C.; Anderson, Michael L., Remote address translation in a multiprocessor system.
  53. Scott, Steven L., Remote translation mechanism for a multi-node system.
  54. Sheets, Kitrick; Hastings, Andrew B., Remote translation mechanism for a multinode system.
  55. Sheu, John Te-Jui; Cohen, Ernest S.; Hendel, Matthew D.; Wang, Landy; Vega, Rene Antonio; Nanavati, Sharvil A., Scalability of virtual TLBs for multi-processor virtual machines.
  56. Dinker, Darpan; Eckhardt, Andrew David; Ouye, Darryl Manabu; O'Krafka, Brian Walter; Cohen, Earl T.; McWilliams, Thomas M., Scalable database management software on a cluster of nodes using a shared-distributed flash memory.
  57. Klausler, Peter M., Scheduling synchronization of programs running as streams on multiple processors.
  58. Sheets,Kitrick; Williams,Josh; Gettler,Jonathan; Piatz,Steve; Hastings,Andrew B.; Hill,Peter; Bravatto,James G.; Kohn,James R.; Titus,Greg, Scheduling synchronization of programs running as streams on multiple processors.
  59. Hagersten, Erik E., Selective address translation in coherent memory replication.
  60. Okochi,Toshio; Shonai,Toru; Hamanaka,Naoki; Irie,Naohiko; Akashi,Hideya, Shared memory multiprocessor system.
  61. Lee, Jaejin; Kim, Junghyun, Shared virtual memory management apparatus for providing cache-coherence.
  62. O'Krafka, Brian Walter; Koster, Michael John; Dinker, Darpan; Cohen, Earl T.; McWilliams, Thomas M., Sharing data fabric for coherent-distributed caching of multi-node shared-distributed flash memory.
  63. Sheets, Kitrick, Sharing memory within an application using scalable hardware resources.
  64. Hagersten Erik E. ; Hill Mark D., Skewed finite hashing function.
  65. Krishnan, Manavalan; Dinker, Darpan; George, Johann, Slave consistency in a synchronous replication environment.
  66. Steiss, Donald E., System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions.
  67. Leinberger, William J.; Kowalski, Bobby Jim; Denny, Ronald R., System and method for managing addresses in a computing system.
  68. Talluri, Madhusudhan; Khalidi, Yousef A., System and method for message transmission between network nodes connected by parallel links.
  69. Faanes, Gregory J.; Lundberg, Eric P.; Scott, Steven L.; Baird, Robert J., System and method for processing memory instructions using a forced order queue.
  70. McWilliams, Thomas M.; Cohen, Earl T.; Bodwin, James M.; Bruening, Ulrich, System including a fine-grained memory and a less-fine-grained memory.
  71. McWilliams, Thomas M.; Cohen, Earl T.; Bodwin, James M.; Bruening, Ulrich, System including a fine-grained memory and a less-fine-grained memory.
  72. McWilliams, Thomas M.; Cohen, Earl T.; Bodwin, James M.; Bruening, Ulrich, System including a fine-grained memory and a less-fine-grained memory.
  73. Molloy, Stephen Arthur; Chun, Dexter Tamio, Systems and methods for providing improved latency in a non-uniform memory architecture.
  74. Molloy, Stephen Arthur; Chun, Dexter Tamio, Systems and methods for providing improved latency in a non-uniform memory architecture.
  75. Hogdal,Gregory; Eldridge,John, Systems and methods for replicating virtual memory on a host computer and debugging using replicated memory.
  76. Hogdal,Gregory; Eldridge,John R., Systems and methods for replicating virtual memory on a host computer and debugging using replicated memory.
  77. Hogdal,Gregory; Eldridge,John R., Systems and methods for replicating virtual memory on a host computer and debugging using replicated memory.
  78. Hogdal, Gregory; Eldridge, John R., Systems and methods for replicating virtual memory on a host computer and debugging using the replicated memory.
  79. Tkacik, Thomas E.; Cannon, Charles E.; Covey, Carlin R.; Hartley, David H.; Ziolowski, Rodney D., Virtualized local storage.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로