초록 ▼

A digital parallel processing system wherein a plurality of nodes communicate via messages sent over an interconnection network. Messages are maintained in strict chronological order even though sent by nodes where several sources are generating messages simultaneously. A network adapter is describe

A digital parallel processing system wherein a plurality of nodes communicate via messages sent over an interconnection network. Messages are maintained in strict chronological order even though sent by nodes where several sources are generating messages simultaneously. A network adapter is described for interconnecting the processor and its associated memory to a network over a bus. The adapter includes an adapter associated memory programmable into a plurality of functional areas, said functional areas including a send FIFO for storing and forwarding messages to said network from said processor; a stack list for queueing in strict message order activation commands for said send FIFO; and an adapter program area for storing adapter program instructions which control the storing of messages to said send FIFO; and control means responsive to said stack list for executing said adapter program instructions in said strict message order without processor intervention.

대표청구항 ▼

[ We claim:] [14.] Method for controlling the transfer of messages from a nodal processor and its associated memory through a network adapter to an interconnection network, said messages including direct memory access (DMA) messages and immediate messages being transferred under control of activatio

[ We claim:] [14.] Method for controlling the transfer of messages from a nodal processor and its associated memory through a network adapter to an interconnection network, said messages including direct memory access (DMA) messages and immediate messages being transferred under control of activation commands, comprising the steps of:storing said DMA messages to said associated memory of said nodal processor;storing said immediate messages in an adapter memory within said network adapter;storing activation commands for said DMA and immediate messages in a send FIFO stacked list within said network adapter;sequentially accessing said send FIFO stacked list to control the storing of said DMA and immediate messages to a send FIFO buffer; andtransferring said DMA and immediate messages from said send FIFO buffer to said interconnection network in sequential order.