초록 ▼

A digital computing system includes a first and second processor clocked for locked step operation. A shared memory stores a linear block codeword across a plurality of byte-wide memory devices. The codeword includes a first dataword and a second dataword. Each of the first and second datawords incl

A digital computing system includes a first and second processor clocked for locked step operation. A shared memory stores a linear block codeword across a plurality of byte-wide memory devices. The codeword includes a first dataword and a second dataword. Each of the first and second datawords includes an equal plurality of databits and each includes an equal plurality of checkbits associated therewith. First error detection and correction logic connected to the first processor receives the first dataword and checkbits associated therewith of the codeword addressed by the first processor and a second dataword and checkbits associated therewith of the codeword addressed by the second processor. First error detection and correction logic detects and/or corrects errors in the codeword. Second error detection and correction logic connected to the second processor receives the second dataword and checkbits associated therewith of the codeword addressed by the second processor and the first dataword and checkbits associated therewith of the codeword addressed by the first processor. The second error detection and correction logic detects and/or corrects errors in the codeword.

대표청구항 ▼

[ What is claimed is:] [1.] A fault-tolerant, fail passive digital computing system, said system comprising:a processor;a memory for storing at least one linear block codeword across a plurality of byte-wide memory devices, said codeword including a dataword and a plurality of checkbits associated t

[ What is claimed is:] [1.] A fault-tolerant, fail passive digital computing system, said system comprising:a processor;a memory for storing at least one linear block codeword across a plurality of byte-wide memory devices, said codeword including a dataword and a plurality of checkbits associated therewith;a databus comprising a plurality of byte-wide partitions, the databus coupling the processor to the memory; and,an error detection and correction means connected to said processor and said memory on said databus for receiving said at least one linear block codeword from said memory or said processor, said error detection and correction means including a syndrome generator having an H matrix for detecting and correcting any single bit error in said linear block codeword transported on said databus such that any byte-wide errors in said linear block codeword are confined to one of said plurality of byte-wide partitions.