초록 ▼

An integrated circuit (2210) provides on a single chip for use with a first processor (106) off-chip, the following combination: first terminals (of 2232) for first processor-related signals and defining a first data width (32-bit), second terminals for external bus-related signals (PCI), third term

An integrated circuit (2210) provides on a single chip for use with a first processor (106) off-chip, the following combination: first terminals (of 2232) for first processor-related signals and defining a first data width (32-bit), second terminals for external bus-related signals (PCI), third terminals for memory-related signals (of 2258), and a DRAM memory controller (2250) connected to the third terminals. Further on chip is provided an arbiter circuit (2230), a bus bridge circuit (2236) coupled to the DRAM memory controller and to the second terminals, the bus bridge (2236) also coupled to the arbiter (2230), a second processor (2224) having a second data width (16-bit), and a bus interface circuit (2220) coupling the second data width of the second processor (2224) to the first data width. The bus interface circuit (2220) further has bus master and bus slave circuitry coupled between the second processor (2224) and the arbiter circuit (2230). The bus bridge (2236), the bus interface (2220) and the first terminals and the DRAM memory controller (2250) have datapaths selectively interconnected in response to the arbiter circuit (2230). Other devices, systems and methods are also disclosed.

대표청구항 ▼

[ What is claimed is:] [1.] An integrated circuit comprising on a single chip for a first processor off-chip:first terminals for first processor-related signals and defining a first data width;second terminals for external bus-related signals;third terminals for memory-related signals;a DRAM memory

[ What is claimed is:] [1.] An integrated circuit comprising on a single chip for a first processor off-chip:first terminals for first processor-related signals and defining a first data width;second terminals for external bus-related signals;third terminals for memory-related signals;a DRAM memory controller connected to said third terminals;an arbiter circuit;a bus bridge circuit coupled to said DRAM memory controller and to said second terminals, said bus bridge also coupled to said arbiter;a second processor having a second data width which is a different data width than said first data width;a bus interface circuit coupling the second data width of said second processor to the first data width, said bus interface circuit further having bus master and bus slave circuitry coupled between said second processor and said arbiter circuit; andsaid bus bridge, said bus interface and said first terminals and said DRAM memory controller having datapaths selectively interconnected in response to said arbiter circuit.