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Process for production of thin layers of semiconductor material 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/76
  • H01L-021/265
  • H01L-021/425
출원번호 US-0080783 (1998-05-18)
발명자 / 주소
  • Egloff Richard
출원인 / 주소
  • Philips Electronics North America Corporation
대리인 / 주소
    Fox
인용정보 피인용 횟수 : 72  인용 특허 : 5

초록

Thin layers of semiconductor material having a high degree of surface uniformity are produced by: implantion of deuterium ions into a body of semiconductor material to form a buried region of high stress, the buried region defining a thin outer region of the body; attaching a stiffening carrier to t

대표청구항

[ What I claim as my invention is:] [1.] A method of forming a thin layer of semiconductor material, the method comprising:(a) implanting a species of ions through a surface of a body of semiconductor material to form a buried region of high stress in the body, the buried region defining a thin oute

이 특허에 인용된 특허 (5)

  1. Kwo Jueinai R. (Somerset County NJ), Method for low temperature growth of epitaxial silicon and devices produced thereby.
  2. Li Jianming (Beijing CNX), Method of making silicon material with enhanced surface mobility by hydrogen ion implantation.
  3. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
  4. Pankove Jacques I. (Boulder CO) Wu Chung P. (Trenton NJ), Silicon light emitting device and a method of making the device.
  5. Horning Robert D. (Burnsville MN) Stratton Thomas G. (Roseville MN) Saathoff Deidrich J. (Burnsville MN), Wafer bonding enhancement technique.

이 특허를 인용한 특허 (72)

  1. Francois J. Henley ; Michael A. Brayan ; William G. En, Cleaving process to fabricate multilayered substrates using low implantation doses.
  2. Henley,Francois J.; Bryan,Michael A.; En,William G., Cleaving process to fabricate multilayered substrates using low implantation doses.
  3. Francois J. Henley ; Nathan Cheung, Controlled cleavage process and device for patterned films.
  4. Henley, Francois J.; Cheung, Nathan, Controlled cleavage process and device for patterned films.
  5. Francois J. Henley ; Nathan W. Cheung, Controlled cleavage process and resulting device using beta annealing.
  6. Henley, Francois J.; Cheung, Nathan, Controlled cleavage process using pressurized fluid.
  7. Henley, Francois J.; Cheung, Nathan W., Controlled cleaving process.
  8. Henley,Francois J.; Cheung,Nathan W., Controlled cleaving process.
  9. Henley,Francois J.; Cheung,Nathan W., Controlled cleaving process.
  10. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  11. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  12. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  13. Henley,Francois J.; Cheung,Nathan W., Controlled process and resulting device.
  14. Tiwari, Sandip; Kumar, Arvind, Dense backplane cell for configurable logic.
  15. Narayanan, Sundar; Ramkumar, Krishnaswamy, Deuterium incorporated nitride.
  16. Henley, Francois J.; Cheung, Nathan W., Gettering technique for wafers made using a controlled cleaving process.
  17. Henley, Francois J.; Cheung, Nathan W., Gettering technique for wafers made using a controlled cleaving process.
  18. Couillard, James G.; Gadkaree, Kishor P.; Mach, Joseph F., Glass-based SOI structures.
  19. Couillard, James G.; Gadkaree, Kishor P.; Mach, Joseph F., Glass-based SOI structures.
  20. Couillard,James G.; Gadkaree,Kishor P.; Mach,Joseph F., Glass-based SOI structures.
  21. Couillard,James G.; Gadkaree,Kishor P.; Mach,Joseph F., Glass-based SOI structures.
  22. Couillard,James G.; Gadkaree,Kishor P.; Mach,Joseph F., Glass-based SOI structures.
  23. Couillard,James Gregory; Gadkaree,Kishor Purushottam; Mach,Joseph Frank, Glass-based SOI structures.
  24. Joly, Jean-Pierre; Ulmer, Laurent; Parat, Guy, Integrated circuit on high performance chip.
  25. Henley, Francois J., Layer transfer of films utilizing controlled propagation.
  26. Henley, Francois J., Layer transfer of films utilizing controlled shear region.
  27. Tiwari, Sandip, Low temperature semiconductor layering and three-dimensional electronic circuits using the layering.
  28. Faris,Sadeg M., MEMS and method of manufacturing MEMS.
  29. Francois J. Henley ; Nathan W. Cheung, Method and device for controlled cleaving process.
  30. Henley, Francois J.; Cheung, Nathan W., Method and device for controlled cleaving process.
  31. Henley,Francois J.; Cheung,Nathan, Method and device for controlled cleaving process.
  32. Sanchez, Loïc, Method and device for monitoring a heat treatment of a microtechnological substrate.
  33. Henley, Francois J., Method and structure for fabricating solar cells using a thick layer transfer process.
  34. Aspar,Bernard; Lagache,Chrystelle, Method for cutting a block of material and forming a thin film.
  35. Fournel, Franck; Moriceau, Hubert; Lagahe, Christelle, Method for making a stressed structure designed to be dissociated.
  36. Deguet, Chrystel; Clavelier, Laurent, Method for making a thin-film element.
  37. Aspar, Bernard; Lagahe, Christelle; Ghyselen, Bruno, Method for making thin layers containing microcomponents.
  38. Iwamoto, Takashi, Method for manufacturing piezoelectric device with a composite piezoelectric substrate.
  39. Tauzin, Aurélie; Dechamp, Jérôme; Mazen, Frédéric; Madeira, Florence, Method for preparing thin GaN layers by implantation and recycling of a starting substrate.
  40. Nakano, Masatake; Yokokawa, Isao; Mitani, Kiyoshi, Method for producing bonded wafer and bonded wafer.
  41. Nguyen, Nguyet-Phuong; Cayrefourcq, Ian; Lagahe-Blanchard, Christelle; Bourdelle, Konstantin; Tauzin, Aurélie; Fournel, Franck, Method for self-supported transfer of a fine layer by pulsation after implantation or co-implantation.
  42. Nguyen, Nguyet-Phuong; Cayrefourcq, Ian; Lagahe-Blanchard, Christelle, Method of catastrophic transfer of a thin film after co-implantation.
  43. Cayrefourcq,Ian; Mohamed,Nadia Ben; Lagahe Blanchard,Christelle; Nguyen,Nguyet Phuong, Method of detaching a thin film at moderate temperature after co-implantation.
  44. Tauzin, Aurélie; Faure, Bruce; Garnier, Arnaud, Method of detaching a thin film by melting precipitates.
  45. Brüderl, Georg; Eichler, Christoph; Strauss, Uwe, Method of fabricating a quasi-substrate wafer and semiconductor body fabricated using such a quasi-substrate wafer.
  46. Faris,Sadeg M., Method of fabricating multi layer devices on buried oxide layer substrates.
  47. Deguet, Chrystel; Clavelier, Laurent; Dechamp, Jerome, Method of transferring a thin film onto a support.
  48. Fournel, Franck, Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer.
  49. Wasshuber,Christoph; Joyner,Keith A., Methods and apparatus for inducing stress in a semiconductor device.
  50. Ries, Michael J.; Libbert, Jeffrey Louis; Lottes, Charles R., Methods for preparing layered semiconductor structures.
  51. Moriceau, Hubert; Rayssac, Olivier; Cartier, Anne-Marie; Aspar, Bernard, Multilayer structure with controlled internal stresses and making same.
  52. Malik, Igor J.; Kang, Sien G.; Fuerfanger, Martin; Kirk, Harry; Flat, Ariel; Current, Michael Ira; Ong, Philip James, Non-contact etch annealing of strained layers.
  53. Bryan, Michael A.; Kai, James K., Nozzle for cleaving substrates.
  54. Bryan, Michael A., Particle distribution method and resulting structure for a layer transfer process.
  55. Moriceau, Hubert; Bruel, Michel; Aspar, Bernard; Maleville, Christophe, Process for the transfer of a thin film.
  56. Moriceau,Hubert; Bruel,Michel; Aspar,Bernard; Maleville,Christophe, Process for the transfer of a thin film.
  57. Moriceau, Hubert; Bruel, Michel; Aspar, Bernard; Maleville, Christophe, Process for the transfer of a thin film comprising an inclusion creation step.
  58. Henley, Francois J.; Brailove, Adam, Race track configuration and method for wafering silicon solar substrates.
  59. Faris,Sadeg M., Selectively bonded thin film layer and substrate layer for processing of useful devices.
  60. Takafuji, Yutaka; Itoga, Takashi, Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate.
  61. Takafuji, Yutaka; Itoga, Takashi, Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate.
  62. Itoga, Takashi; Ogawa, Yasuyuki, Semiconductor device with recessed registration marks partially covered and partially uncovered.
  63. Henley, Francois J.; Cheung, Nathan W., Silicon-on-silicon hybrid wafer assembly.
  64. Takafuji,Yutaka; Itoga,Takashi, Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device.
  65. Moriceau, Hubert; Aspar, Bernard; Margail, Jacques, Stacked structure and production method thereof.
  66. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  67. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  68. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  69. Ishihara, Shigenori; Kawase, Nobuo, Surface treatment method, manufacturing method of semiconductor device, and manufacturing method of capacitive element.
  70. Brailove, Adam; Liu, Zuqin; Henley, Francois J.; Lamm, Albert J., Techniques for forming thin films by implantation with reduced channeling.
  71. Tauzin,Aur��lie, Thin film splitting method.
  72. Faris,Sadeg M, Vertical integrated circuits.
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