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Vertical dual loadlock chamber 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B65G-001/10
출원번호 US-0749611 (1996-11-18)
발명자 / 주소
  • Blum Rick
  • Fairbairn Kevin
  • Lane Christopher
출원인 / 주소
  • Applied Materials, Inc.
대리인 / 주소
    Patterson & Associates
인용정보 피인용 횟수 : 69  인용 특허 : 20

초록

A vacuum loadlock is provided for housing a pair of wafers in proper alignment for concurrent processing. In one embodiment, a single chamber loadlock is provided with a gas diffuser disposed therein to decrease venting times within the loadlock. In another embodiment, a dual chamber loadlock is pro

대표청구항

[ What is claimed is:] [1.] An apparatus for loading wafers into a processing system, comprising:(a) a chamber disposed adjacent to the processing system, the chamber comprising:(i) an enclosure;(ii) a transfer region which communicates between the enclosure and the processing system through an aper

이 특허에 인용된 특허 (20)

  1. Prentakis Antonios E. (Cambridge MA), Apparatus and method for loading and unloading wafers.
  2. Maeda Kazuo (Tokyo JPX) Ohira Kouichi (Tokyo JPX) Hirose Mitsuo (Tokyo JPX), Apparatus for manufacturing semiconductor device.
  3. Matsushita Yoshinari (Hirakata JPX) Fukumoto Kenji (Hirakata JPX), Chemical vapor deposition reaction apparatus having isolated reaction and buffer chambers.
  4. Thomas Michael E. (Milpitas CA) van de Van Everhardus P. (Cupertino CA) Broadbent Eliot K. (San Jose CA), Gas-based backside protection during substrate processing.
  5. Mizuno Shigeru (Fuchu JPX) Katsumata Yoshihiro (Fuchu JPX) Takahashi Nobuyuki (Fuchu JPX), Integrated module multi-chamber CVD processing system and its method for processing substrates.
  6. Mizuno Shigeru (Kawasaki JPX) Katsumata Yoshihiro (Fujiyoshida JPX) Takahashi Nobuyuki (Mitaka JPX), Integrated module multi-chamber CVD processing system and its method for processing substrates.
  7. Lorimer D\Arcy H. (Pismo Beach CA), Low particulate slit valve system and method for controlling same.
  8. Krueger Gordon P. (San Jose CA), Micro-enviroment load lock.
  9. Maydan Dan (Los Altos Hills CA) Somekh Sasson (Redwood City CA) Wang David N. (Cupertino CA) Cheng David (San Jose CA) Toshima Masato (San Jose CA) Harari Isaac (Mountain View CA) Hoppe Peter D. (Sun, Multichamber integrated process system.
  10. Bramhall ; Jr. Robert B. (Gloucester MA) Cloutier Richard M. (Salisbury MA) Laber Albert P. (Revere MA) Muka Richard S. (Topsfield MA), Sealing apparatus for a vacuum processing system.
  11. Wu Hong J. (Hsin-chu TWX), Single semiconductor wafer transfer method and manufacturing system.
  12. Tepman Avi (Cupertino CA) Andrews Dana L. (Mountain View CA), Slit valve apparatus and method.
  13. Cheng David (San Jose CA) Zhang Wesley W. (Burlingame CA), System and method for detecting the center of an integrated circuit wafer.
  14. Walker Delroy (Springdale MD) Zihmer Joseph (Frederick MD) Furches Danny (Columbia MD) Garmer Christopher J. (Rockville MD), System for transferring articles between controlled environments.
  15. Iwai Hiroyuki (Sagamihara JPX) Tanifuji Tamotsu (Yamato JPX) Asano Takanobu (Yokohama JPX) Okura Ryoichi (Kanagawa-ken JPX), Treatment apparatus.
  16. Lowrance Robert B. (Los Gatos CA), Two-axis magnetically coupled robot.
  17. Toshima Masato (Campbell CA), Vacuum chamber slit valve.
  18. Davis ; Jr. James C. (Carlisle MA), Valve.
  19. Szalai Laszlo (Campbell CA), Valve closure mechanism for semiconductor deposition apparatus.
  20. Takanabe Eiichiro (Sagamihara JPX) Suzuki Takeo (Iruma JPX) Noguchi Tadataka (Kitakyushu JPX), Vertical heat-treating apparatus and heat-treating process by using the vertical heat-treating apparatus.

이 특허를 인용한 특허 (69)

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  2. Howald,Arthur M.; Kuthi,Andras; Bailey, III,Andrew D.; Berney,Butch, Apparatus and methods for minimizing arcing in a plasma processing chamber.
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  4. Shirai Hidenobu,JPX, Chamber apparatus for processing semiconductor devices.
  5. Sasaki Yoshiaki,JPX ; Asakawa Teruo,JPX, Controlling gas in a multichamber processing system.
  6. Lee,Jae Chull; Berkstresser,David, Curved slit valve door with flexible coupling.
  7. Lee, Jae-Chull; Kurita, Shinichi; White, John M.; Anwar, Suhail, Decoupled chamber body.
  8. Borean, Christophe; Delcarri, Jean-Luc, Device and process for chemical vapor phase treatment.
  9. Kurita, Shinichi; Blonigan, Wendell T., Double dual slot load lock chamber.
  10. Avi Tepman ; Donald J. K. Olgado ; Allen L. D'Ambra, Dual buffer chamber cluster tool for semiconductor wafer processing.
  11. Clarke Andrew Peter, Dual degas/cool loadlock cluster tool.
  12. Clarke, Andrew Peter, Dual degas/cool loadlock cluster tool.
  13. Kurita, Shinichi; Blonigan, Wendell T.; Hosokawa, Akihiro, Dual substrate loadlock process equipment.
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  22. Nowak, Thomas; Rocha-Alvarez, Juan Carlos; Kaszuba, Andrzej; Hendrickson, Scott A.; Ho, Dustin W.; Baluja, Sanjeev; Cho, Tom; Chang, Josephine; M'Saad, Hichem, High efficiency UV curing system.
  23. Kurita, Shinichi; Blonigan, Wendell T.; Tanase, Yoshiaki, Large area substrate transferring method for aligning with horizontal actuation of lever arm.
  24. Klomp, Albert Jan Hendrik; Hoogkamp, Jan Frederik; Vugts, Josephus Cornelius Johannes Antonius; Livesey, Robert Gordon; Franssen, Johannes Hendrikus Gertrudis, Load lock and method for transferring objects.
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  54. Nakamura Gen,JPX, Substrate conveying system.
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  63. Gage, Christopher; Chua, Lee Peng, Transferring heat in loadlocks.
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  68. Chan, Soon Chye, Wafer handling system for a loadlock.
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