초록 ▼

An electronic delay circuit (10) useful for the delayed initiation of detonators illustrates several novel features that may be combined, including a novel oscillator (34), a programmable timer circuit (32) and a run control circuit (46). The oscillator (34) generates a clock signal determined by th

An electronic delay circuit (10) useful for the delayed initiation of detonators illustrates several novel features that may be combined, including a novel oscillator (34), a programmable timer circuit (32) and a run control circuit (46). The oscillator (34) generates a clock signal determined by the rate of discharge of a capacitor (34a) relative to a reference voltage REF. A second capacitor (34b) is charged to a voltage that exceeds REF, and when the first capacitor (34a) falls below REF, an internal signal is generated and the capacitors are switched, so that the first capacitor gets charged while the second is discharged. A latch (34f) produces clock pulses in response to the internal signals. The programmable timer circuit (32) includes a ripple counter (38) and a program bank (40) that loads a count in the counter upon initialization. Each stage of the counter (38) has separate inputs for set and clear signals, and the program bank (40) has a setting circuit and a clearing circuit for each counter stage. Each clearing circuit generates a signal of fixed duration and each setting circuit can generate a signal of two different durations, one of which exceeds the clear signal. During programming, the set signal of short or long duration is chosen and, in loading the counter, the longer of the set signal or the clear signal determines the state of the counter stage. The run control circuit (46) controls a gate (34h) that permits oscillator pulses to increment the counter (38), but closes gate (34h) should a temporary loss in power occur thus preventing the timer (32) from being re-initialized.

대표청구항 ▼

[ What is claimed is:] [9.] A lock-out electronic timer circuit, powered by a power supply, for issuing a timer circuit output signal after the expiration of a programmed time delay following the receipt of an electrical initiation signal, the timer circuit comprising:(a) an oscillator circuit which

[ What is claimed is:] [9.] A lock-out electronic timer circuit, powered by a power supply, for issuing a timer circuit output signal after the expiration of a programmed time delay following the receipt of an electrical initiation signal, the timer circuit comprising:(a) an oscillator circuit which is responsive to a RESET ST(b) a ripple counter configured to count reference clock pulses and to produce the timer output signal when a predetermined count is reached;(c) a clock gate through which the ripple counter receives the reference clock pulses when the clock gate receives a CLKEN signal; and(d) a control circuit for generating a CLKEN signal, the control circuit comprising a control bank and a lock-out cell and being responsive to a RESET STwherein the control bank is responsive to the lock-out cell and the lock-out cell is thereafter responsive to the control bank, wherein the lock-out cell and an initial RESET ST