초록 ▼

An ATM reassembly controller is disclosed that optimizes the utilization of host memory space and hardware resources such as I/O bus bandwidth, host memory bandwidth, memory system bandwidth and CPU resources. The system combines, whenever possible, the PDU status, PDU data and pointers to the host

An ATM reassembly controller is disclosed that optimizes the utilization of host memory space and hardware resources such as I/O bus bandwidth, host memory bandwidth, memory system bandwidth and CPU resources. The system combines, whenever possible, the PDU status, PDU data and pointers to the host memory data buffers into a large burst write to the status queue. In addition, multiple status bundles are packed into a host memory buffer for efficient use of memory. An additional benefit of combining and packing information is that CPU resources are conserved by having combined the information the CPU must access into to a contiguous memory area.

대표청구항 ▼

[ What is claimed is:] [1.] An ATM reassembly controller for reassembling ATM cells into protocol data units for storage in main memory having main memory buffers and reassembly descriptor lists, comprising:an input port for receiving an ATM cell;a processor, operatively coupled to the input port, f

[ What is claimed is:] [1.] An ATM reassembly controller for reassembling ATM cells into protocol data units for storage in main memory having main memory buffers and reassembly descriptor lists, comprising:an input port for receiving an ATM cell;a processor, operatively coupled to the input port, for identifying a virtual channel for the ATM cell, stripping a payload from the ATM cell associated with the identified virtual channel, and building a protocol data unit descriptor header for a reassembled protocol data unit constructed with the payload from the ATM cell;a local memory buffer, coupled to the processor, for storing the payload and protocol data unit descriptor header;a memory manager, operatively coupled to the processor, for assigning pointers to the local memory buffer and determining when the local memory buffer is full; anda memory access controller, operatively coupled to the local memory buffer, for writing the content of the local memory buffer in a single burst to host memory for accessing by an application in response to determining that the local memory buffer is full.