초록 ▼

A bit synchronization circuit receives polarity-judged output signal and a level-judged output signal that are produced through demodulation of a 2-value FSK or 4-value FSK transmission signal. Flip-flop circuits and an exclusive-OR circuit generate a second sampling output by sampling and delaying

A bit synchronization circuit receives polarity-judged output signal and a level-judged output signal that are produced through demodulation of a 2-value FSK or 4-value FSK transmission signal. Flip-flop circuits and an exclusive-OR circuit generate a second sampling output by sampling and delaying the polarity-judged output signal. Flip-flop circuits and an exclusive-NOR circuit generate a third sampling signal having a given temporal relationship with the second sampling output by sampling and delaying the level-judged output signal. AND circuits supply a correction signal to a counter circuit when levels of the second and third sampling outputs and a phase signal indicating a correction period of the counter circuit satisfy a given relationship. In response to the correction signal, the counter circuit corrects its count so as to produce a clock signal having a rate that is equal to a transmission rate of the transmission signal.

대표청구항 ▼

[ What is claimed is:] [1.] A bit synchronization method comprising the steps of:receiving a polarity-judged output signal obtained by detecting polarity variations of a demodulation signal obtained by demodulating a transmission signal that is modulated according to 2-value FSK or 4-value FSK and a

[ What is claimed is:] [1.] A bit synchronization method comprising the steps of:receiving a polarity-judged output signal obtained by detecting polarity variations of a demodulation signal obtained by demodulating a transmission signal that is modulated according to 2-value FSK or 4-value FSK and a level-judged output signal obtained by detecting level variations of the demodulating signal;generating a first sampling output by sampling and delaying a state variation of the polarity-judged output signal with a sampling signal;generating a phase signal indicating a period during which a count of a counter circuit needs to be corrected;generating, when levels of the first sampling output and the phase signal satisfy a given relationship, a correction signal indicating that the count of the counter circuit should be corrected; andin response to the correction signal, adding to or subtracting from the count of the counter circuit a number corresponding to an integral multiple of a reference clock period so that a clock signal that is output from the counter circuit has a rate equal to a transmission rate of the transmission signal.