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[미국특허] Method for assembling an integrated circuit chip package having at least one semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/56
출원번호 US-0166056 (1998-10-02)
발명자 / 주소
  • Banks Donald R.
  • Pofahl Ronald G.
  • Sylvester Mark F.
  • Petefish William G.
  • Fischer Paul J.
출원인 / 주소
  • Gore Enterprise Holdings, Inc.
대리인 / 주소
    Genco, Jr.
인용정보 피인용 횟수 : 52  인용 특허 : 5

초록 ▼

The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integ

대표청구항 ▼

[ We claim:] [1.] A method for assembling an integrated circuit chip package having an organic package substrate and an integrated circuit chip, said method comprising the following steps:providing an organic package substrate having,A) a metal core having at least one clearance formed therethrough,

이 특허에 인용된 특허 (5) 인용/피인용 타임라인 분석

  1. Mortimer ; Jr. William P. (New Castle DE), Polytetrafluoroethylene film.
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  2. Bowman Jeffery B. (Flagstaff AZ) Hubis Daniel E. (Elkton MD) Lewis James D. (Flagstaff AZ) Newman Stephen C. (Flagstaff AZ) Staley Richard A. (Flagstaff AZ), Process for producing a high strength porous polytetrafluoroethylene product having a coarse microstructure.
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  3. Gore Robert W. (Newark DE), Process for producing porous products.
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  4. Ota Kazuhide (Okazaki JPX) Abe Susumu (Toyota JPX), Process for producing ultra-fine ceramic particles.
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  5. Ameen Joseph G. (Bear DE) Mortimer ; Jr. William P. (Conowingo MD) Yokimcus Victor P. (Newark DE), Thermally conductive interface.
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이 특허를 인용한 특허 (52) 인용/피인용 타임라인 분석

  1. Hoffmeyer, Mark K.; Mikhail, Amanda E.; Sinha, Arvind K., Area array device connection structures with complimentary warp characteristics.
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  2. Ho, Chung W., Cavity down flip chip BGA.
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  3. Lee, Hung-Jen; Chang, Shu-Ming; Chiang, Chen-Han; Liu, Tsang-Yu; Ho, Yen-Shih, Chip package structure and manufacturing method thereof.
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  4. Akerling Gershon ; Anderson James M. ; Spargo John W. ; Tang Benjamin, Chip-to-board connection assembly and method therefor.
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  5. Okugawa, Yoshitaka; Tsukurimichi, Keiichi; Kawaguchi, Hitoshi, Circuit board manufacturing method, semiconductor manufacturing apparatus, circuit board and semiconductor device.
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  6. Thomas H. Distefano, Compliant semiconductor chip package with fan-out leads and method of making same.
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  7. Ramalingam Suresh, Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material.
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  8. Ramalingam,Suresh; Murali,Venkatesan; Cook,Duane, Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials.
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  9. Walmsley, Robert G; Zhang, Zhuqing; Wu, Jennifer; Bernard, Sheldon A; Choy, Silam J, Device including interposer between semiconductor and substrate.
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  10. Paul J. Fischer ; Robin E. Gorrell ; Mark F. Sylvester, Dimensionally stable core for use in high density chip packages and a method of fabricating same.
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  11. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Encapsulated semiconductor package.
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  12. Yang, Chun Chieh; Cao, Hong Xi; Kuo, Chia Tai; Chen, Chih Li; Chen, Cheng Fa; Horng, Ji Bin, High heat dissipating LED having a porous material layer.
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  13. Grieder, Andrew; Lazar, Alexander, High temperature eutectic solder ball attach.
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  14. Chun-Chi Lee TW; Jaw-Shiun Hsieh TW; Yao-Hsin Feng TW; Shyh-Ing Wu TW; Kuan-Neng Liao TW; Chin-Pei Tien TW, Laser method for forming vias.
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  15. O'Brien, James N.; Zou, Lian-Cheng; Sun, Yunlong; Fahey, Kevin P.; Wolfe, Michael J.; Baird, Brian W.; Harris, Richard S., Laser segmented cutting.
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  16. O'Brien, James N.; Zou, Lian-Cheng; Sun, Yunlong; Fahey, Kevin P.; Wolfe, Michael J.; Baird, Brian W.; Harris, Richard S., Laser segmented cutting, multi-step cutting, or both.
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  17. Japp Robert M. ; Poliks Mark D., Low CTE power and ground planes.
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  18. Thomas Sunil, Low stress method and apparatus for underfilling flip-chip electronic devices.
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  19. Jonathon G. Greenwood, Making chip size semiconductor packages.
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  20. Howerton, Jeff; Childers, David; Johansen, Brian; Alpay, Mehmet Emin, Method and apparatus for laser drilling holes with Gaussian pulses.
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  21. Howerton, Jeff; Childers, David; Johansen, Brian; Alpay, Mehmet Emin, Method and apparatus for laser drilling holes with Gaussian pulses.
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  22. Maa Chong-Ren,TWX ; Lin Albert,TWX ; Biar Jin-Chyuan,TWX, Method for improving the reliability of underfill process for a chip.
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  23. Japp, Robert M.; Poliks, Mark D., Method for making printed circuit board having low coefficient of thermal expansion power/ground plane.
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  24. Deshpande,Nitin A.; Sane,Sandeep B., Method for reducing assembly-induced stress in a semiconductor die.
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  25. Sylvester Mark F. ; Noddin David B., Method of increasing package reliability by designing in plane CTE gradients.
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  26. Sohn, Keungjin; Ikeguchi, Nobuyuki; Ryu, Joung-Gul; Park, Ho-Sik; Lee, Sang-Youp; Shin, Joon-Sik; Park, Jung-Hwan, Method of manufacturing and insulating sheet.
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  27. Matsuhira,Tsutomu; Adachi,Hideaki; Hayashi,Keiichiro; Nishigawa,Tadahiro; Koizumi,Nobukazu, Method of manufacturing electric device.
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  28. Chen, Chien Hua; Haluzak, Charles C.; Michael, Donald, Methods for hermetic sealing of post media-filled MEMS package.
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  29. O'Connor, Michael; Springett, Thomas W.; Ward-Dolkas, Paul C., Microdisplay packaging system.
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  30. O'Connor, Michael; Springett, Thomas W.; Ward-Dolkas, Paul C., Microdisplay packaging system.
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  31. O'Connor,Michael; Springett,Thomas W.; Ward Dolkas,Paul C., Microdisplay packaging system.
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  32. Alcoe, David J.; Dalrymple, Thomas W.; Gaynes, Michael A.; Stutzman, Randall J., Module with adhesively attached heat sink.
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  33. Alcoe, David J.; Dalrymple, Thomas W.; Gaynes, Michael A.; Stutzman, Randall J., Module with adhesively attached heat sink.
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  34. Wen-chou Vincent Wang ; Thomas J. Massingill ; Yasuhito Takahashi ; Lei Zhang, Modules with pins and methods for making modules with pins.
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  35. George F. Raiser ; Bob Sundahl ; Ravi Mahajan, Partial underfill for flip-chip electronic packages.
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  36. Raiser, George F.; Sundahl, Bob; Mahajan, Ravi, Partial underfill for flip-chip electronic packages.
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  37. Ramalingam, Suresh; Vodrahalli, Nagesh; Costello, Michael J.; Loke, Mun Leong; Mahajan, Ravi V., Process for assembling an integrated circuit package having a substrate vent hole.
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  38. Ito, Mutsuyoshi; Ohta, Kentaro, Process for producing semiconductor package and structure thereof.
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  39. Cook Duane ; Murali Venkatesan ; Ramalingam Suresh ; Vodrahalli Nagesh, Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state.
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  40. Cook, Duane; Ramalingam, Suresh, Process line for underfilling a controlled collapse.
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  41. Sasaki, Taishi; Ishihara, Mikio, Semiconductor device.
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  42. Imori, Yoshihisa, Semiconductor device and method for manufacturing the same.
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  43. Tanaka, Naotaka; Kawano, Kenya; Nagai, Akira; Tasaki, Koji; Yasuda, Masaaki, Semiconductor device and multilayer substrate therefor.
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  44. Nishiyama, Tomohiro; Tago, Masamoto, Semiconductor device, wiring substrate, and method for manufacturing wiring substrate.
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  45. Weygan Teddy D.,PHX ; Arabe Ferdinand B.,PHX ; Arguelles Ronaldo M.,PHX, Substrate for accommodating warped semiconductor devices.
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  46. Chen, Chien-Hua; Haluzak, Charles C.; Michael, Donald, System and methods for hermetic sealing of post media-filled MEMS package.
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  47. Satoh, Masayuki, System in package with built-in test-facilitating circuit.
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  48. Lau,Daniel K.; Law,Edward L. T., Thermal enhanced package for block mold assembly.
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  49. Atwood Eugene R. ; Benenati Joseph A. ; DiGiacomo Giulio ; Quinones Horatio, Thermal enhancement approach using solder compositions in the liquid state.
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  50. Atwood, Eugene R.; Benenati, Joseph A.; DiGiacomo, Giulio; Quinones, Horatio, Thermal enhancement approach using solder compositions in the liquid state.
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  51. Haley Kevin J. ; Delaplane Niel C. ; Mahajan Ravindranath V. ; Starkston Robert ; Gealer Charles A. ; Krauskopf Joseph C., Thermal interface thickness control for a microprocessor.
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  52. Akram Salman ; Jiang Tongbi, Void-free underfill of surface mounted chips.
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