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Method of forming a semiconductor device having dual inlaid structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0921293 (1997-08-29)
발명자 / 주소
  • Wetzel Jeffrey T.
  • Stankus John J.
출원인 / 주소
  • Motorola, Inc.
인용정보 피인용 횟수 : 88  인용 특허 : 3

초록

A method for forming semiconductor device (1) that includes providing a substrate (10) having a metal interconnect (12), depositing a via interlevel dielectric (ILD) layer (20) over the substrate (10) and the metal interconnect (12), etching the via ILD layer (20) to form a via (30) over the metal i

대표청구항

[ What is claimed is:] [1.] A method for forming a semiconductor device comprising the steps of:providing a substrate having a metal interconnect;depositing a via interlevel dielectric layer over the substrate and the metal interconnect;etching the via interlevel dielectric layer to form a via over

이 특허에 인용된 특허 (3)

  1. Beyer Klaus D. (Poughkeepsie NY) Guthrie William L. (Poughkeepsie NY) Makarewicz Stanley R. (New Windsor NY) Mendel Eric (Poughkeepsie NY) Patrick William J. (Newburgh NY) Perry Kathleen A. (Lagrange, Chem-mech polishing method for producing coplanar metal/insulator films on a substrate.
  2. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  3. Chow Ming-Fea (Poughquagh NY) Guthrie William L. (Hopewell Junction NY) Kaufman Frank B. (Amawalk NY), Method of forming fine conductive lines, patterns and connectors.

이 특허를 인용한 특허 (88)

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