초록 ▼

An asynchronous mode transfer (ATM) switch conducting switching based upon the calculation of weights for entries corresponding to cells in an input queue to achieve a high throughput rate which avoids head of line blocking. The switch includes a cell scheduler driven by the iterative resolution of

An asynchronous mode transfer (ATM) switch conducting switching based upon the calculation of weights for entries corresponding to cells in an input queue to achieve a high throughput rate which avoids head of line blocking. The switch includes a cell scheduler driven by the iterative resolution of a traffic matrix formed by highest priority entries for each of a plurality of output ports queued in each of a plurality input queues each having separate virtual queues corresponding to the output ports. Conflicts in the matrix are resolved according to weight so that one entry per one row is chosen to be transmitted in parallel. Selection of winning entries from among a group of conflicting entries during any step are resolved by selecting the heaviest weighted entry and leaving the remaining ports maximum satisfactory transmission opportunities. The input queue communicates with the cell scheduler to assign priority level entries corresponding to highest priority cells which are queued in the input queue for each output port. The calculated weight for each entry during an iteration is a function of its priority level and the priority level of all other entries in a common row and column. A subsequent iteration is conducted without the winner and without all other entries in the same row and column as the winner.

대표청구항 ▼

[ What is claimed is:] [1.] An asynchronous mode transmission switch comprising:a plurality of input ports;a plurality of output ports, each in switched connection as a destination port for a cell transmitted from any one of said plurality of input ports;an input queue for receiving and queuing ATM

[ What is claimed is:] [1.] An asynchronous mode transmission switch comprising:a plurality of input ports;a plurality of output ports, each in switched connection as a destination port for a cell transmitted from any one of said plurality of input ports;an input queue for receiving and queuing ATM cells from said plurality of input ports for scheduling to designated ones of said plurality of output ports; anda matrix cell scheduler, said scheduler forming a first traffic matrix having rows corresponding to said input ports and columns corresponding to said output ports, said first matrix including entries corresponding to cells queued in said input queue and iteratively choosing entries to be routed to their designated output ports during a next transmission timing by successively selecting a winning entry during each step of said iteratively choosing while removing rows and columns including winning entries from further contention during subsequent steps.